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CS82C59AZ Arkusz danych(PDF) 6 Page - Intersil Corporation |
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CS82C59AZ Arkusz danych(HTML) 6 Page - Intersil Corporation |
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6 / 22 page  6 FN2784.5 March 17, 2006 Interrupt Request Register (IRR) and In-Service Register (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (lRR) and the In- Service Register (lSR). The IRR is used to indicate all the interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels which are currently being serviced. Priority Resolver This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the corresponding bit of the lSR during the INTA sequence. Interrupt Mask Register (IMR) The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority. Interrupt (INT) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286 input levels. Interrupt Acknowledge (INTA) INTA pulses will cause the 82C59A to release vectoring information onto the data bus. The format of this data depends on the system mode ( µPM) of the 82C59A. Data Bus Buffer This 3-state, bidirectional 8-bit buffer is used to interface the 82C59A to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer. Read/Write Control Logic The function of this block is to accept output commands from the CPU. It contains the Initialization Command Word (lCW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 82C59A to be transferred onto the Data Bus. Chip Select (CS) A LOW on this input enables the 82C59A. No reading or writing of the device will occur unless the device is selected. Write (WR) A LOW on this input enables the CPU to write control words (lCWs and OCWs) to the 82C59A. Read (RD) A LOW on this input enables the 82C59A to send the status of the Interrupt Request Register (lRR), In-Service Register (lSR), the Interrupt Mask Register (lMR), or the interrupt level (in the poll mode) onto the Data Bus. A0 This input signal is used in conjunction with WR and RD signals to write commands into the various command registers, as well as to read the various status registers of the chip. This line can be tied directly to one of the system address lines. The Cascade Buffer/Comparator This function block stores and compares the IDs of all 82C59As used in the system. The associated three I/O pins (CAS0 - 2) are outputs when the 82C59A is used as a master and are inputs when the 82C59A is used as a slave. As a master, the 82C59A sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section “Cascading the 82C59A”.) Interrupt Sequence The powerful features of the 82C59A in a microcomputer system are its programmability and the interrupt routine addressing capability. The latter allows direct or indirect jumping to the specified interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. 82C59A 82C59A |
Podobny numer części - CS82C59AZ |
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Podobny opis - CS82C59AZ |
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