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ADSP-BF549BBCZ-ENG Arkusz danych(PDF) 2 Page - Analog Devices |
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ADSP-BF549BBCZ-ENG Arkusz danych(HTML) 2 Page - Analog Devices |
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2 / 68 page  Rev. PrE | Page 2 of 68 | April 2007 ADSP-BF542/4/8/9 Preliminary Technical Data TABLE OF CONTENTS Features ................................................................. 1 Memory ................................................................ 1 Peripherals ............................................................. 1 Table Of Contents .................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3 Low-Power Architecture ......................................... 4 System Integration ................................................ 4 ADSP-BF542/4/8/9 Processor Peripherals ................... 4 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers ................................................ 10 Real-Time Clock ................................................. 11 Watchdog Timer ................................................ 11 Timers ............................................................. 12 Up/Down Counter and Thumbwheel Interface .......... 12 Serial Ports (SPORTs) .......................................... 12 Serial Peripheral Interface (SPI) Ports ...................... 12 UART Ports (UARTs) .......................................... 13 Controller Area Network (CAN) ............................ 13 TWI Controller Interface ...................................... 13 Ports ................................................................ 14 Pixel Compositor (PIXC) ...................................... 14 Enhanced Parallel Peripheral Interface (EPPI) ........... 14 USB On-The-Go Dual-Role Device Controller ........... 15 ATA/ATAPI–6 Interface ...................................... 15 Keypad Interface ................................................. 15 Secure Digital (SD)/SDIO Controller ....................... 15 Code Security ..................................................... 15 Media Transceiver Mac Layer (MXVR) .................... 15 Voltage Regulation .............................................. 17 Clock Signals ...................................................... 17 Booting Modes ................................................... 19 Instruction Set Description .................................... 20 Development Tools .............................................. 21 Designing an Emulator-Compatible Processor Board (Target) ................................................. 21 Related Documents .............................................. 21 Pin Descriptions .................................................... 22 Specifications ........................................................ 31 Operating Conditions ........................................... 31 Electrical Characteristics ....................................... 32 ESD Sensitivity ................................................... 32 Absolute Maximum Ratings ................................... 33 Package Information ............................................ 33 Timing Specifications ........................................... 34 Power Dissipation ............................................... 58 Test Conditions .................................................. 58 Environmental Conditions .................................... 59 400-Ball BGA Pinout ............................................... 60 Outline Dimensions ................................................ 66 Ordering Guide ..................................................... 67 REVISION HISTORY Revision PrE: Corrections and additions to PrD: • Many individual line changes throughout datasheet • Specific Peripherals for Processors table added • Replace Voltage Regulator Circuit diagram • Table 10 - processor pin multiplexing reworked • Table 11 - Pin Descriptions reworded • Absolute Maximum Rating reworked • HDMA A/C Timing-Host Read Cycle and Write Cycle added • Outline dimensions specified |
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