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AD9236BCPZRL7-80 Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD9236BCPZRL7-80
Szczegółowy opis  12-Bit, 80 MSPS, 3 V A/D Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD9236BCPZRL7-80 Arkusz danych(HTML) 8 Page - Analog Devices

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AD9236
Rev. B | Page 8 of 36
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
Signal-to-Noise and Distortion (SINAD)1
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Aperture Delay (t
Effective Number of Bits (ENOB)
A
)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
)
Aperture Uncertainty (Jitter, tJ
(
)
02
.
6
76
.
1
= SINAD
ENOB
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
Signal-to-Noise Ratio (SNR)1
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious Free Dynamic Range (SFDR)1
The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the deviation
of the actual transition from that point.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Gain Error
The first code transition should occur at an analog value
½ LSB above negative full scale. The last transition should occur
at an analog value 1½ LSB below positive full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
Temperature Drift
The clock rate at which parametric testing is performed.
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at T
)
Output Propagation Delay (tPD
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
MIN
or TMAX.
Power Supply Rejection Ratio
Out-of-Range Recovery Time
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Total Harmonic Distortion (THD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
1 AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).


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