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AM49PDL640AG Arkusz danych(PDF) 11 Page - SPANSION |
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11 / 69 page November 20, 2003 Am49PDL640AG 9 P R E L I M I NARY ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am49PDL640 A G a 70 N T TAPE AND REEL T= 7 inches S = 13 inches TEMPERATURE RANGE N = Light Industrial (–25 °C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations pSRAM VENDOR Blank = Etron a= Si-7 PROCESS TECHNOLOGY G = 0.17 µm Pseudo SRAM DEVICE DENSITY A= 16 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49PDL640AG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM Valid Combinations Order Number Package Marking Am49PDL640AG70N T, S M49000001Y Am49PDL640AG85N M49000001Z Am49PDL640AGa70N M49000004F Am29PDL640AGa85N M49000004G |
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