©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74ABT573 Rev. 1.4

7

SOIC package.

Notes:

12. This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described

switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)

13. This specification is guaranteed but not tested. The limits represent propagation delays with 250pF load capacitors

in place of the 50pF load capacitors in the standard AC load.

14. Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate

but not tested.

15. This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same

pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the

guaranteed specification. This specification is guaranteed but not tested.

specification is guaranteed but not tested.

Capacitance

Note:

Symbol

Parameter

8 Outputs

8 Outputs

Units

Max.

Max.

(14)

Pin to Pin Skew, HL Transitions

1.0

1.5

ns

(14)

Pin to Pin Skew, LH Transitions

1.0

1.5

ns

(15)

Duty Cycle, LH–HL Skew

1.4

3.5

ns

(14)

Pin to Pin Skew, LH/HL Transitions

1.5

3.9

ns

(16)

Device to Device Skew LH/HL

Transitions

2.0

4.0

ns

Symbol

Parameter

Conditions

Typ.

Units

Input Capacitance

5

pF

(17)

Output Capacitance

9

pF