Zakładka z wyszukiwarką danych komponentów |
|
ISL5217KI Arkusz danych(PDF) 10 Page - Intersil Corporation |
|
ISL5217KI Arkusz danych(HTML) 10 Page - Intersil Corporation |
10 / 43 page 10 FN6004.3 July 8, 2005 modulator. The maximum phase step that can occur in one clock is ±180 degrees. Table 1 provides the change in phase weighting of the input bits. Shaping Filter The shaping filter provides the necessary pulse shaping required on the input data to implement various QASK and shaped FM modulation formats. Two identical shaping filters (one each for the I and Q paths) are provided. The shaping filter architecture uses a NCO controlled interpolating FIR, capable of 4, 8, or 16 interpolation phases. The number of interpolation phases, (IP) is loaded into FIR Control (0xd, bits 1:0). The span of the impulse response of the polyphase filter can vary from 4-16 data samples. The desired sample Data Span, (DS) value minus one is loaded into FIR Control (0xd, bits 7:4). Thus, the required number of coefficients (or filter span) becomes: The Interpolation Phase also determines the rate to compute a polyphase output by selecting the appropriate timing from the Sample Rate NCO to drive the shaping filter at 4x, 8x, or 16x the input sample rate. The Data Span selects the number of samples to convolve. Each convolution requires DS reference clocks for each phase of the filter. An output is calculated (IP) times for each input sample. To allow sufficient processing time for each output, the reference clock must be as follows: Conversely, the input sample rate requires: where fCLK is the frequency of the reference clock, IP is the shaping filter interpolate rate; and DS is the number of data samples in the filter span. For example, if fCLK = 104MHz, the filter span is 16 samples, and the interpolation rate is 16, then the maximum input sample rate, fS is 104/256 = 406.25kHz. Table 2 shows several examples of calculations for FIR input sample rates based on master reference clock rate, number of data samples, and interpolation rate. The data exits the shaping filters at the interpolated rate. The shaping filters have programmable coefficients which must be loaded via the microprocessor interface. The QPUC supports loading coefficients for two shaping filters, with FIR Control (0xd, bit 8) selecting the active filter. The I and Q shaping filters are identical and may be loaded simultaneously or separately, allowing for different gains and responses through the filter if desired. Because 16 interpolation phases are possible, the coefficients are structured in sets of 16, one set for each phase of the shaping filter. The convolution algorithm sequentially steps through each of these phases, beginning with phase 0. The coefficients for the shaping filters are generated by designing the prototype filter at the interpolated rate. The coefficients are then divided into interpolation phases by taking every nth tap of the prototype filter and storing the coefficient as an element of a coefficient set. The IP value determines the addressing interval through the prototype filter to create the coefficient sets for the filter phases. The first coefficient set begins at address 0. The next coefficient set begins at address 1 and continues in a like manner for the remaining coefficient sets. For a 16 tap, interpolate-by-4 filter, the calculations for filter 1 are: Polyphase output 0 = (C0*D[n]) + (C4*D[n-1]) + (C8*D[n-2]) + (C12*D[n-3]) Polyphase output 1 = (C1*D[n]) + (C5*D[n-1]) + (C9*D[n-2]) + (C13*D[n-3]) Polyphase output 2 = (C2*D[n]) + (C6*D[n-1]) + (C10*D[n-2]) + (C14*D[n-3]) Polyphase output 3 = (C3*D[n]) + (C7*D[n-1]) + (C11*D[n-2]) + (C15*D[n-3]) If FIR Control (8) is set the calculations for filter 2 are: Polyphase output 0 = (D0*D[n]) + (D4*D[n-1]) + (D8*D[n-2]) + (D12*D[n-3]) TABLE 1. PHASE WEIGHTING d φ(nT)/dt DEGREES/SAMPLE 1000 0000 0000 0000 -180 0000 0000 0000 0000 0 0111 1111 1111 1111 ~+180 # Coefficients = (DS)(IP) (EQ. 2) CLK DS () IP () f S () ≥ (EQ. 3) f S f CLK [IP () ⁄ DS () ] ≤ (EQ. 4) TABLE 2. EXAMPLE CALCULATIONS EXAMPLE fCLK DS IP MAX fS 1 104MHz 16 16 104/256 = 406.25kHz 2 104MHz 16 8 104/128 = 812.5kHz 3 104MHz 16 4 104/64 = 1.625MHz 4 104MHz 10 4 104/40 = 2.600MHz 5 104MHz 8 4 104/32 = 3.250MHz 6 104MHz 4 4 104/16 = 6.500MHz TABLE 3. FIR CONTROLS IP STARTING ADDRESS W/FIR CONTROL (8) = ‘0’ STARTING ADDRESS W/FIR CONTROL (8) = ‘1’ 40 8 80 8 16 0 128 ISL5217 |
Podobny numer części - ISL5217KI |
|
Podobny opis - ISL5217KI |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |