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ISL21400IU8Z-TK Arkusz danych(PDF) 5 Page - Intersil Corporation

Numer części ISL21400IU8Z-TK
Szczegółowy opis  Programmable Temperature Slope Voltage Reference
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Producent  INTERSIL [Intersil Corporation]
Strona internetowa  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL21400IU8Z-TK Arkusz danych(HTML) 5 Page - Intersil Corporation

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5
FN8091.0
December 14, 2006
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed
(Note 3)
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing
30% of VCC, until SDA exits
the 30% to 70% of VCC
window (Note 3)
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC
during a STOP condition, to
SDA crossing 70% of VCC
during the following START
condition (Note 3)
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC
crossing (Note 3)
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC
crossing (Note 3)
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA
falling edge; both crossing
70% of VCC (Note 3)
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VCC to SCL
falling edge crossing 70% of
VCC (Note 3)
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VCC window, to SCL
rising edge crossing 30% of
VCC (Note 3)
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge
crossing 70% of VCC to SDA
entering the 30% to 70% of
VCC window (Note 3)
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge
crossing 70% of VCC, to SDA
rising edge crossing 30% of
VCC (Note 3)
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL
falling edge; both crossing
70% of VCC (Note 3)
1300
ns
tDH
Output Data Hold Time
From SCL falling edge
crossing 30% of VCC, until
SDA enters the 30% to 70%
of VCC window (Note 3)
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VCC
(Note 3)
20 +
0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VCC
(Note 3)
20 +
0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
(Note 4)
10
400
pF
Serial Interface Specification (for SCL, SDA, A0, A1, A2 unless specified otherwise) (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 2)
MAX
UNITS
ISL21400


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