Zakładka z wyszukiwarką danych komponentów |
|
ISL6117 Arkusz danych(PDF) 5 Page - Intersil Corporation |
|
ISL6117 Arkusz danych(HTML) 5 Page - Intersil Corporation |
5 / 12 page 5 February 6, 2007 Description and Operation The members of this family are single power supply distribution controllers for generic hot swap applications across the +2.5V to +12V supply range. The ISL6115 is targeted for +12V switching applications whereas the ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V applications. Each IC has a hardwired undervoltage (UV) threshold level approximately 17% lower than the stated voltages. These ICs feature a highly accurate programmable overcurrent (OC) detecting comparator, programmable current regulation (CR) with programmable time delay to latch off, and programmable soft-start turn-on ramp all set with a minimum of external passive components. The ICs also include severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as a near dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, the ICs have a UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft- start mode protecting the supply rail from sudden in-rush current. At turn-on, the external gate capacitor of the N-Channel MOSFET is charged with a 10 μA current source resulting in a programmable ramp (soft-start turn-on). The internal ISL6115 charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +5V, for the other three ICs the gate drive voltage is limited to the chip bias voltage, VDD. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20μA current source and the controller enters the current limit time to latch- off period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2) for CTIM capacitor value and resulting nominal current limited time out to latch-off duration placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V, signaling that the time out period has expired an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load. This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10 μs. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time out period. Upon a UV condition the PGOOD signal will pull low when tied high through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to VDD once the time out period expires. See Figures 12 to 16 for waveforms relevant to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high. CURRENT REGULATION DURATION/POWER GOOD CTIM Charging Current CTIM_ichg0 VCTIM = 0V 16 20 23 μA CTIM Fault Pull-Up Current (Note 3) -20 - mA Current Limit Time-Out Threshold Voltage CTIM_Vth CTIM Voltage 1.3 1.8 2.3 V Power Good Pull Down Current PG_Ipd VOUT = 0.5V - 8 - mA Electrical Specifications VDD = 12V, TA = TJ = 0°C to +85°C, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS TABLE 1. RISET RESISTOR NOMINAL OC VTH 10k Ω 200mV 4.99k Ω 100mV 2.5k Ω 50mV 750 Ω 15mV NOTE: Nominal Vth = RISET x 20μA. TABLE 2. CTIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD 0.022 μF2ms 0.047 μF4.4ms 0.1 μF9.3ms NOTE: Nominal time-out period = CTIM x 93kΩ. ISL6115, ISL6116, ISL6117, ISL6120 |
Podobny numer części - ISL6117 |
|
Podobny opis - ISL6117 |
|
|
Link URL |
Polityka prywatności |
ALLDATASHEET.PL |
Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |