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ADC14C065 Arkusz danych(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC14C065
Szczegółowy opis  14-Bit, 65/80/95/105 MSPS A/D Converter
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC14C065 Arkusz danych(HTML) 3 Page - National Semiconductor (TI)

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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
5V
IN+
Differential analog input pins. The differential full-scale input
signal level is 2V
P-P with each input pin signal centered on a
common mode voltage, V
CM.
6V
IN-
2V
RP
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor
should be placed between V
RP and VRN as close to the pins as
possible, anda1µF capacitor should be placed in parallel.
V
RP and VRN should not be loaded. VCMO may be loaded to
1mA for use as a temperature stable 1.5V reference.
It is recommended to use V
CMO to provide the common mode
voltage, V
CM, for the differential analog inputs, VIN+ and VIN−.
32
V
CMO
1V
RN
31
V
REF
Reference Voltage. This device provides an internally
developed 1.2V reference. When using the internal reference,
V
REF should be decoupled to AGND with a 0.1 µF anda1µF
low equivalent series inductance (ESL) capacitor .
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
DIGITAL I/O
11
CLK
The clock input pin.
The analog input is sampled on the rising edge of the clock
input.
12
OF/DCS
This is a four-state pin controlling the input clock mode and
output data format.
OF/DCS = V
A, output data format is 2’s complement without
duty cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without
duty cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V
A, output data is 2’s complement with duty
cycle stabilization applied to the input clock
OF/DCS = (1/3)*V
A, output data is offset binary with duty cycle
stabilization applied to the input clock.
30
PD
This is a two-state input controlling Power Down.
PD=V
A, Power Down is enabled and power dissipation is
reduced.
PD = AGND, Normal operation.
www.national.com
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