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LM26001_0609 Arkusz danych(PDF) 10 Page - National Semiconductor (TI) |
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LM26001_0609 Arkusz danych(HTML) 10 Page - National Semiconductor (TI) |
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10 / 17 page  Operation Description (Continued) on, enable, or UVLO recovery, an internal 2.3 µA (typical) current charges the soft-start capacitor. During soft-start, the error amplifier output voltage is controlled by both the soft- start voltage and the feedback loop. As the SS pin voltage ramps up, the duty cycle increases proportional to the soft- start ramp, causing the output voltage to ramp up. The rate at which the duty cycle increases depends on the capaci- tance of the soft-start capacitor. The higher the capacitance, the slower the output voltage ramps up. The soft-start ca- pacitor value can be calculated with the following equation: Where tss is the desired soft-start time and Iss is the soft- start source current. During soft-start, current limit and syn- chronization remain in effect, while sleep mode and fre- quency foldback are disabled. Soft-start mode ends when the SS pin voltage reaches 1.23V typical. At this point, output voltage control is transferred to the FB pin and the SS pin is discharged. CURRENT LIMIT The peak current limit is set internally by directly measuring peak inductor current through the internal switch. To ensure accurate current sensing, VIN should be bypassed with a minimum 1µF ceramic capacitor placed directly at the pin. When the inductor current reaches the current limit thresh- old, the internal FET turns off immediately allowing inductor current to ramp down until the next cycle. This reduction in duty cycle corresponds to a reduction in output voltage. The current limit comparator is disabled for less than 100ns at the leading edge for increased immunity to switching noise. Because the current limit monitors peak inductor current, the DC load current limit threshold varies with inductance and frequency. Assuming a minimum current limit of 1.85A, maxi- mum load current can be calculated as follows: Where Iripple is the peak-to-peak inductor ripple current, calculated as shown below: To find the worst case (lowest) current limit threshold, use the maximum input voltage and minimum current limit speci- fication. During high over-current conditions, such as output short circuit, the LM26001 employs frequency foldback as a sec- ond level of protection. If the feedback voltage falls below the short circuit threshold of 0.9V, operating frequency is re- duced, thereby reducing average switch current. This is especially helpful in short circuit conditions, when inductor current can rise very high during the minimum on-time. Frequency reduction begins at 20% below the nominal fre- quency setting. The minimum operating frequency in fold- back mode is 71 kHz typical. If the FB voltage falls below the frequency foldback threshold during frequency synchronized operation, the SYNC function is disabled. Operating frequency versus FB voltage in short circuit conditions is shown in the typical performance char- acteristics section. In conditions where the on time is close to minimum (less than 200nsec typically), such as high input voltage and high switching frequency, the current limit may not function prop- erly. This is because the current limit circuit cannot reduce the on-time below minimum which prevents entry into fre- quency foldback mode. There are two ways to ensure proper current limit and foldback operation under high input voltage conditions. First, the operating frequency can be reduced to increase the nominal on time. Second, the inductor value can be increased to slow the current ramp and reduce the peak over-current. FREQUENCY ADJUSTMENT AND SYNCHRONIZATION The switching frequency of the LM26001 can be adjusted between 150 kHz and 500 kHz using a single external resistor. This resistor is connected from the FREQ pin to ground as shown in the typical application. The resistor value can be calculated with the following empirically derived equation: R FREQ = (6.25 x 10 10)xf SW -1.042 The switching frequency can also be synchronized to an external clock signal using the SYNC pin. The SYNC pin allows the operating frequency to be varied above and below the nominal frequency setting. The adjustment range is from 30% above nominal to 20% below nominal. External syn- chronization requires a 1.2V (typical) peak signal level at the SYNC pin. The FREQ resistor must always be connected to initialize the nominal operating frequency. The operating fre- quency is synchronized to the falling edge of the SYNC input. When SYNC goes low, the high-side switch turns on. This allows any duty cycle to be used for the sync signal when synchronizing to a frequency higher than nominal. When synchronizing to a lower frequency, however, there is a minimum duty cycle requirement for the SYNC signal, given in the equation below: 20179451 FIGURE 5. Swtiching Frequency vs R FREQ www.national.com 10 |
Podobny numer części - LM26001_0609 |
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Podobny opis - LM26001_0609 |
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