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AD5724R Arkusz danych(PDF) 8 Page - Analog Devices

Numer części AD5724R
Szczegółowy opis  Quad 12-Bit Serial Input Unipolar/Bipolar Voltage Output DAC
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Strona internetowa  http://www.analog.com
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AD5726
Rev. 0 | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1
VOUTD 2
VOUTC 3
VREFN 4
CLRSEL
16
CLR
15
LDAC
14
NC
13
VREFP 5
VOUTB 6
VOUTA 7
CS
12
SCLK
11
SDIN
10
AVSS 8
GND
9
NC = NO CONNECT
TOP VIEW
(Not to Scale)
AD5726
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AVDD
Positive Analog Supply Pin. Voltage ranges from 5 V to 15 V
2
VOUTD
Buffered Analog Output Voltage of DAC D.
3
VOUTC
Buffered Analog Output Voltage of DAC C.
4
VREFN
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output.
Allowable range is AVSS to VREFP − 2.5 V.
5
VREFP
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage.
Allowable range is AVDD − 2.5 V to VREFN + 2.5 V.
6
VOUTB
Buffered Analog Output Voltage of DAC B.
7
VOUTA
Buffered Analog Output Voltage of DAC A.
8
AVSS
Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V.
9
GND
Ground Reference Pin.
10
SDIN
Serial Data Input. Data must be valid on the rising edge of SCLK. This input is ignored when CS is high.
11
SCLK
Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
12
CS
Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin is logically OR’ed with
the SCLK input and disables the serial data input when high.
13
NC
No Internal Connection.
14
LDAC
Active Low, Asynchronous Load DAC Input. The data currently contained in the serial input register is
transferred out to the DAC data registers on the falling edge of LDAC, independent of CS. Input data must
remain stable while LDAC is low.
15
CLR
Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or midscale (0x800),
depending on the state of CLRSEL. The data in the serial input register is unaffected by this control.
16
CLRSEL
Determines the action of CLR. If high, a clear command sets the internal DAC registers to midscale (0x800).
If low, the registers are set to zero (0x000).


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