ADATE207BBP datasheet(4/36 Pages) AD

Numer części	ADATE207BBP

Szczegółowy opis	Quad Pin Timing Formatter

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ADATE207

Rev. 0 | Page 4 of 36

AC SPECIFICATIONS

TC = 85°C ± 5°C, VDD = 2.5 V, unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ

Max

Unit

CLOCK INPUTS

Master Clock (MCLK) Frequency

100

MHz

MCLK Duty Cycle

46

50

54

%

DRIVE OUTPUTS

Output Pulse Width

Timing error < ±125 ps

1

ns

COMPARE INPUTS

Minimum Comparison Window Width

1.25

ns

Minimum Detectable Glitch Width

1.25

ns

EDGE PERFORMANCE

Retrigger Time

2.5

ns

Edge Delay

0

Lesser of 4 T0 cycles

or 163.8 μs

Vernier Resolution

39.06

ps

Vernier Timing DNL

−150

+150

ps

Vernier Timing INL

−150

+150

ps

Vernier Temperature Coefficient

4

ps/°C

Edge Jitter

MCLK jitter 5 ps rms

20

ps rms

CONTROL AND STATUS REGISTER (CSR) INTERFACE

Clock Period

10

ns

Setup Time (tBSU)

MCLK

1.1

ns

Hold Time (tBH)

MCLK

0.5

ns

Clock to Output (tBCO)

MCLK

2.5

7.0

ns

Clock to Tristate (tBCZ)

2.3

4.2

ns

Clock to Data Valid from Tristate (tBCZV)

0

7.0

ns

DIGITAL INPUTS

Set Up (tISU)

MCLK

1.7

ns

Hold Time (tIH)

MCLK

0.5

ns

DIGITAL OUTPUTS

Clock to Output (tOCO)

MCLK

0.7

1.6

ns

JTAG PORTS

JTAG Clock Period

100

ns

Setup Time (tSSU)

JTAG CLOCK

50

ns

Hold Time (tSH)

JTAG CLOCK

50

ns

Clock to Output (tSCO)

JTAG CLOCK

50

ns

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