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SM65MLVD205AD Arkusz danych(PDF) 6 Page - Texas Instruments

Numer części SM65MLVD205AD
Szczegółowy opis  MULTIPOINT-LVDS LINE DRIVER AND RECEIVER
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SM65MLVD205AD Arkusz danych(HTML) 6 Page - Texas Instruments

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DRIVER SWITCHING CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
SN65MLVD200A, SN65MLVD202A
SN65MLVD204A, SN65MLVD205A
SLLS573 – DECEMBER 2003
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tpLH
Propagation delay time, low-to-high-level output
2
2.5
3.5
ns
tpHL
Propagation delay time, high-to-low-level output
2
2.5
3.5
ns
tr
Differential output signal rise time
2
2.6
3.2
ns
See Figure 5
tf
Differential output signal fall time
2
2.6
3.2
ns
tsk(p)
Pulse skew (|tpHL– tpLH|)
30
150
ps
tsk(pp)
Part-to-part skew
0.9
ns
tjit(per)
Period jitter, rms (1 standard deviation)(2)
50 MHz clock input(3)
2
3
ps
tjit(pp)
Peak-to-peak jitter(2)(4)
100 Mbps 215-1 PRBS input(5)
55
150
ps
tPHZ
Disable time, high-level-to-high-impedance output
4
7
ns
tPLZ
Disable time, low-level-to-high-impedance output
4
7
ns
See Figure 6
tPZH
Enable time, high-impedance-to-high-level output
4
7
ns
tPZL
Enable time, high-impedance-to-low-level output
4
7
ns
(1)
All typical values are at 25
°C and with a 3.3-V supply voltage.
(2)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(3)
tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(4)
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(5)
tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
over recommended operating conditions unless otherwise noted
TYP(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1)
tPLH
Propagation delay time, low-to-high-level output
2
3.6
6
ns
tPHL
Propagation delay time, high-to-low-level output
2
3.6
6
ns
tr
Output signal rise time
1
2.3
ns
tf
Output signal fall time
CL = 15 pF, See Figure 10
1
2.3
ns
Type 1
100
300
ps
tsk(p)
Pulse skew (|tpHL– tpLH|)
Type 2
300
500
ps
tsk(pp)
Part-to-part skew(2)
1
ns
tjit(per)
Period jitter, rms (1 standard deviation)(3)
50 MHz clock input(4)
4
7
ps
Type 1
200
700
ps
tjit(pp)
Peak-to-peak jitter(3)(5)
100 Mbps 215–1 PRBS input(6)
Type 2
225
800
ps
tPHZ
Disable time, high-level-to-high-impedance output
6
10
ns
tPLZ
Disable time, low-level-to-high-impedance output
6
10
ns
See Figure 11
tPZH
Enable time, high-impedance-to-high-level output
10
15
ns
tPZL
Enable time, high-impedance-to-low-level output
10
15
ns
(1)
All typical values are at 25
°C and with a 3.3-V supply voltage.
(2)
HP4194A impedance analyzer (or equivalent)
(3)
Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4)
VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k
samples.
(5)
Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
(6)
VID = 200 mVpp (LVD200A, 202A), VID = 400 mVpp (LVD204A, 205A), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k
samples.
6
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