CDCF5801ADBQ datasheet(8/18 Pages) TI

Numer części	CDCF5801ADBQ

Szczegółowy opis	CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

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JITTER SPECIFICATION

CDCF5801A

SCAS816 – MARCH 2006

over recommended free-air temperature range and V

CC range (unless otherwise noted)

TEST CONDITIONS

PARAMETER

TYP (ps)

MAX (ps)

REFCLK

CLKOUT

MULT[0:1] P[0:2]

NOTES

(MHz)

Period rms (1-sigma jitter, full

25

11

001

20

48

frequency band)

Period p-p

120

225

Cycle to cycle +

70

165

Cycle to cycle -

70

165

RMS phase jitter (accumulated,

80

160

100 kHz-12.5 MHz)

Period rms (1-sigma jitter, full

50

11

001

7

15

frequency band)

Period p-p

37

75

Cycle to cycle +

27

55

Cycle to cycle -

27

55

Phase

RMS phase jitter (accumulated,

27

65

aligner

100 kHz-25 MHz)

running

(CLKOUT

Period rms (1-sigma jitter, full

100

00

010

5

14

tight to

frequency band)

LEADLAG;

Period p-p

30

65

REFCLK

t(jitter)

Cycle to cycle +

tight to

24

55

DLYCTRL).

Cycle to cycle -

24

55

All typical

RMS phase jitter (accumulated,

35

65

values are

100 kHz-40 MHz)

at

VDD = 3.3

Period rms (1-sigma jitter, full

156

00

010

4

8

V,

frequency band)

TA = 25°C.

Period p-p

20

40

Cycle to cycle +

17

40

Cycle to cycle -

17

40

RMS phase jitter (accumulated,

15

35

100 kHz-40 MHz)

Period rms (1-sigma jitter, full

200

01

011

8

15

frequency band)

Period p-p

38

60

Cycle to cycle +

5

55

Cycle to cycle -

35

55

RMS phase jitter (accumulated,

30

60

100 kHz-40 MHz)

8

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