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MCZ33977EGR2 Arkusz danych(PDF) 10 Page - Freescale Semiconductor, Inc

Numer części MCZ33977EGR2
Szczegółowy opis  Single Gauge Driver
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Producent  FREESCALE [Freescale Semiconductor, Inc]
Strona internetowa  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCZ33977EGR2 Arkusz danych(HTML) 10 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
10
Freescale Semiconductor
33977
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
This 33977 is a single-packaged, Serial Peripheral
INterface (SPI) controlled, single stepper motor gauge driver
integrated circuit (IC). This monolithic stepper IC consists of
[deleted two per D. Mortensen] a dual output H-Bridge coil
driver [deleted plural s for accurate tense] and the
associated control logic. The dual H-Bridge driver is used to
automatically control the speed, direction, and magnitude of
current through the coils of a two-phase instrumentation
stepper motor, similar to an MMT-licensed AFIC 6405 of
Switec MS-X 156.xxx motor.
FUNCTIONAL PIN DESCRIPTION
COSINE POSITIVE (COS0+)
The H-Bridge pins linearly drive the sine and cosine coils
of a stepper motor, providing four-quadrant operation.
COSINE NEGATIVE (COS0-)
The H-Bridge pins linearly drive the sine and cosine coils
of a stepper motor, providing four-quadrant operation.
SINE POSITIVE (SIN+)
The H-Bridge pins linearly drive the sine and cosine coils
of a stepper motor, providing four-quadrant operation.
SINE NEGATIVE (SIN-)
The H-Bridge pins linearly drive the sine and cosine coils
of a stepper motor, providing four-quadrant operation.
GROUND (GND)
Ground pins.
CHIP SELECT (CS)
The pin enables communication with the master device.
When this pin is in a logic [0] state, the 33977 is capable of
transferring information to, and receiving information from,
the master. The 33977 latches data in from the Input Shift
registers to the addressed registers on the rising edge of CS.
The output driver on the SO pin is enabled when CS is
logic [0]. When CS is logic high, signals at the SCLK and SI
pins are ignored and the SO pin is tri-stated (high
impedance). CS will only be transitioned from a logic [1] state
to a logic [0] state when SCLK is logic [0]. CS has an internal
pull-up (IUP) connected to the pin, as specified in the section
of the Static Electrical Characteristics Table.
SERIAL CLOCK (SCLK)
SCLK clocks the Internal Shift registers of the 33977
device. The SI pin accepts data into the Input Shift register on
the falling edge of the SCLK signal, while the Serial Output
pin (SO) shifts data information out of the SO Line Driver on
the rising edge of the SCLK signal. It is important that the
SCLK pin be in a logic [0] state whenever the CS makes any
transition.
SCLK has an internal pull down (lDWN), as specified in the
section of the Static Electrical Characteristics Table. When
CS is logic [1], signals at the SCLK and SI pins are ignored
and SO is tri-stated (high impedance). Refer to the data
transfer Timing Diagrams on page 9.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted
out. Those bits are followed by the message bits clocked in
FIFO, when the device is in a daisy chain connection or being
sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
high impedance state until the CS pin is put into a logic low
state.
SERIAL INPUT (SI)
The SI pin is the input of the SPI. Serial input information
is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, beginning with the most
significant bit (MSB). Messages that are not multiples of 16
bits (e.g., daisy chained device messages) are ignored. After
transmitting a 16-bit word, the CS pin must be de-asserted
(logic [1]) before transmitting a new word. SI information is
ignored when CS is in a logic high state.
RETURN TO ZERO (RTZ)
This is a multiplexed output pin for the non-driven coil,
during a Return to Zero (RTZ) event.
VOLTAGE (VDD)
The SPI and logic power supply input will work with 5.0 V
supplies.
RESET (RST)
If the master decides to reset the device, or place it into a
sleep state, the RST pin is driven to a Logic [0]. A Logic [0] on
the RST pin forces all internal logic to the known default state.
This input has an internal active pull-up.
VOLTAGE POWER (VPWR)
This is the power supply pin.


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