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ST78C36ACJ44 Arkusz danych(PDF) 3 Page - Exar Corporation |
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ST78C36ACJ44 Arkusz danych(HTML) 3 Page - Exar Corporation |
3 / 28 page xr ST78C36/36A REV. 5.0.2 ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO 3 PIN DESCRIPTION NAME 44-PLCC PIN # 64-LQFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A10 A2 A1 A0 29 39 41 40 36 46 53 52 I Address Select Lines. A10 places the ECP control/status/data ports at 0x400 offset from the -CS decoded address. D7 D6 D5 D4 D3 D2 D1 D0 9 10 11 12 13 14 15 16 5 6 7 8 9 10 11 12 I/O Data bus. Bi-directional data port. -IOR 43 55 I Active low AT bus I/O Read strobe. -IOW 42 54 I -CS 22 24 I Chip select (active LOW). A LOW at this pin enables the parallel port / CPU data transfer operation. IOCHRDY 18 19 O I/O Channel ready (internal pull-up / three stated active HIGH). This pin goes low when the device requires addition clock cycles for read and write. -IRQ9 -IRQ7 -IRQ5 - 19 - 14 20 18 O Interrupt Request Lines (three stated active low). AEN 17 13 I DMA address enable (active HIGH). When this line is HIGH, the DMA controller has control of the address bus. DRQ3 DRQ2 DRQ1 7 - - 3 63 51 O Active high AT bus DMA ReQuest for channels 3, 2 and 1 (internal pull- down three stated active HIGH). A request is generated by bringing a DRQx line to a HIGH level. A DRQx line is held HIGH until the corre- sponding DMA acknowledge “DACKx*” line goes LOW. -DACK3 -DACK2 -DACK1 8 - - 4 2 47 I DMA Acknowledge signals for channels 3, 2 and 1 (internal pull-up /three stated active low). TC 6 62 I Terminal Count (active HIGH). The ST78C36 terminates the DMA channel when a HIGH pulse is detected. |
Podobny numer części - ST78C36ACJ44 |
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