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ST16C550CQ48 Arkusz danych(PDF) 11 Page - Exar Corporation |
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ST16C550CQ48 Arkusz danych(HTML) 11 Page - Exar Corporation |
11 / 35 page ST16C550 11 Rev. 5.01 DMA Operation The ST16C550 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFO’s in the DMA mode (FCR bit-3). The DMA mode affects the state of the -RXRDY and -TXRDY output pins. The following tables show this: -RXRDY pin: Non-DMA mode DMA mode 1 = FIFO empty 0 to 1 transition when FIFO empties 0 = at least 1 byte 1 to 0 transition when FIFO in FIFO reaches trigger level, or timeout occurs -TXRDYpin: Non-DMA mode DMA mode 1 = at least 1 byte 1 = FIFO is full in FIFO 0 = FIFO empty 0 = FIFO has at least 1 empty location Loop-back Mode The internal loop-back capability allows onboard diag- nostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. In this mode MSR bits 4-7 are also disconnected. However, MCR register bits 0-3 can be used for controlling loop-back diagnostic test- ing. In the loop-back mode -OP1 and -OP2 in the MCR register (bits 0-1) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associ- ated interface pins, and instead are connected together internally (See Figure 4). The -CTS, -DSR, -CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to - DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serial- izes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. In this mode , the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. The interrupts are still controlled by the IER. Figure 3, TYPICAL EXTERNAL CRYSTAL OSCIL- LATOR CONNECTION C1 22-47pF C2 22-47pF Y1 1.8432 - 24 MHz R1 0-120 (Optional) R2 1M XTAL1 XTAL2 |
Podobny numer części - ST16C550CQ48 |
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Podobny opis - ST16C550CQ48 |
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