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TDA1312 Arkusz danych(PDF) 5 Page - NXP Semiconductors |
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TDA1312 Arkusz danych(HTML) 5 Page - NXP Semiconductors |
5 / 13 page July 1993 5 Philips Semiconductors Preliminary specification Stereo continuous calibration DAC (CC-DAC) TDA1312A; TDA1312AT PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input DATAR 2 right data input DATAL 3 left data input GND 4 ground VDD 5 positive supply voltage VOL 6 left channel output VOR 7 right channel output WS 8 word select input Fig.2 Pin configuration. handbook, halfpage 1 2 3 4 8 7 6 5 MGE224 TDA1312 TDA1312AT WS VOR DATAR VOL VDD GND DATAL BCK FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value Iref, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the OUT terminal. The 32 current sources and the spare current source of the TDA1312A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. The TDA1312A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs.4 and 5. Data is placed in the right and left input registers (see Fig.1). The data in the input registers is simultaneously latched in the output registers which control the bit switches. An internal offset voltage VOFF is added to the full scale output voltage VFS; VOFF and VFS are proportional to VDD: Where VDD1/VDD2 = VFS1/VFS2 = VOFF1/VOFF2. |
Podobny numer części - TDA1312 |
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Podobny opis - TDA1312 |
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