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SN74ACT7202LA50DV Arkusz danych(PDF) 1 Page - Texas Instruments

Numer części SN74ACT7202LA50DV
Szczegółowy opis  256 횞 9, 512 횞 9, 1024 횞 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

SN74ACT7202LA50DV Arkusz danych(HTML) 1 Page - Texas Instruments

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SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256
× 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Reads and Writes Can Be Asynchronous
or Coincident
D Organization:
– SN74ACT7200L – 256
× 9
– SN74ACT7201LA – 512
× 9
– SN74ACT7202LA – 1024
× 9
D Fast Data Access Times of 15 ns
D Read and Write Frequencies up to 40 MHz
D Bit-Width and Word-Depth Expansion
D Fully Compatible With the
IDT7200 / 7201 / 7202
D Retransmit Capability
D Empty, Full, and Half-Full Flags
D TTL-Compatible Inputs
D Available in 28-Pin Plastic DIP (NP),
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
description
The SN74ACT7200L, SN74ACT7201LA, and
SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow
and
overflow
of
memory,
and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0
°C
to 70
°C.
Copyright
© 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
VCC
D4
D5
D6
D7
FL /RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
DV OR NP PACKAGE
(TOP VIEW)
32 1 32 31
14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL /RT
RS
EF
XO/HF
Q7
Q6
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
430
15 16 17 18 19
RJ PACKAGE
(TOP VIEW)
20
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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