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TDA8001T Arkusz danych(PDF) 8 Page - NXP Semiconductors |
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TDA8001T Arkusz danych(HTML) 8 Page - NXP Semiconductors |
8 / 24 page 1996 Dec 12 8 Philips Semiconductors Product specification Smart card interface TDA8001 READ MODE When the activation sequence is completed and, after the card has replied its Answer-to-Reset, the TDA8001 will be in the READ mode. Data is exchanged between the card and the microcontroller via the I/O line. WRITE MODE Cards with EPROM memory need a programming voltage (VPP). When it is required to write to the internal memory of the card, the microcontroller sets one of the VPP12.5, VPP15 and VPP21 lines LOW, according to the programming value given in the Answer-to-Reset. VPP rises from 5 V to the selected value with a typical slew rate of 0.38 V/ µs. In order to respect the ISO 7816 slopes, the circuit generates VPP by charging and discharging an internal capacitor. The voltage on this capacitor is then amplified by a power stage gain of 5, powered via an external supply pin VH (30 V max). DEACTIVATION SEQUENCE (see Fig.8) When the session is completed, the microcontroller sets the CMDVCC line to its HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back: • RST falls to LOW and CLK is stopped • I/O(µC) becomes high impedance and VPP falls to 0 V • VCC falls to 0 V. The circuit returns to the IDLE mode on the next rising edge of the clock. PROTECTIONS Main fault conditions are monitored by the circuit: • Short-circuit or overcurrent on VCC • Short-circuit or overcurrent on VPP • Card extraction during transaction • Overheating problem • VSUP drop-out • VDD drop-out. When one of these fault conditions is detected, the circuit pulls the interrupt line OFF to its active LOW state and returns to the FAULT mode. The current on I/O is internally limited to 5 mA. FAULT MODE (see Fig.9) When a fault condition is written to the microcontroller via the OFF line, the circuit initiates a deactivation sequence. After the deactivation sequence has been completed, the OFF line is reset to its HIGH state after the microcontroller has reset the CMDVCC line HIGH. Fig.4 Alarm and delay as a function of VSUP (CDEL fixes the pulse width). handbook, full pagewidth MGG818 VSUP Vth2 + Vhys2 Vth2 Vth3 td VDELAY ALARM |
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Podobny opis - TDA8001T |
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