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LM2506 Arkusz danych(PDF) 11 Page - National Semiconductor (TI) |
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LM2506 Arkusz danych(HTML) 11 Page - National Semiconductor (TI) |
11 / 19 page Functional Description (Continued) TABLE 2. Serializer Input Timing Parameters for RGB Interface Sym. Parameter Min Typ Max Units t SET Data (RGB, DE, VS or HS) to PCLK - Set Time 5 ns t HOLD PCLK to Data (RGB, DE, VS or HS) - Hold Time 5 ns Note 10: Signal rise and fall times are equal to or less than 20ns Note 11: Measurement of signal timing is made using 0.3 x VDDIO for the low sate and 0.7 x VDDIO for the high state. TABLE 3. Deserializer Output Timing Parameters for RGB Interface Sym. Parameter Min Typ Max Units t DVBC Data Valid before PCLK (rise) (Note 9) PCLK = 2 MHz 230 ns PCLK = 13.3 MHz 30 ns t DVAC Data Valid after PCLK (rise) (Note 9) PCLK = 2 MHz 230 ns PCLK = 13.3 MHz 30 ns t PCLK Pixel Clock Period 75.2 500 ns PCLK LOW Pixel Clock Low 50 % PCLK HIGH Pixel Clock High 50 % 20125527 FIGURE 12. Deserializer Mode Output Timing for RGB Interface www.national.com 11 |
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