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LM2506GR Arkusz danych(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części LM2506GR
Szczegółowy opis  Low Power Mobile Pixel Link (MPL) Level 0, 18-bit RGB Display Interface Serializer and Deserializer
Download  19 Pages
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM2506GR Arkusz danych(HTML) 5 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MPL
I
DDZ
Supply Current — Disable
T
A = 25˚C
Power Down Modes
SER
PD*=L
V
DDIO
<12
µA
V
DD/VDDA
<1
2.2
µA
SER
Stop Clock
V
DDIO
<12
µA
V
DD/VDDA
<1
2.2
µA
DES
PD*=L
V
DDIO
<12
µA
V
DD/VDDA
<1
2.2
µA
PD
Power Dissipation
RGB
(Note 6)
SER
8.5
mW
DES
15.3
mW
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
PARALLEL BUS TIMING See
t
SET
Set Up Time
RGB Mode Inputs
Figure 11
5ns
t
HOLD
Hold Time
5
ns
t
RISE
Rise Time
PCLK Output
C
L =15pF,
Figure 2
V
DDIO = 1.74V
7
12
ns
V
DDIO = 3.0V
3
7
ns
t
FALL
Fall Time
V
DDIO = 1.74V
7
11
ns
V
DDIO = 3.0V
2
6
ns
SERIAL BUS TIMING
t
DVBC
Serial Data Valid before
Clock
(Set Time)
DES Input
Figure 1
MC = 80MHz
(Note 9)
1.5
ns
t
DVAC
Serial Data Valid after
Clock
(Hold Time)
1.5
ns
POWER UP TIMING
t
0
SER PLL Lock Counter
4,096
PCLK
cycles
t
1
MC Pulse Width Low
180
MC
cycles
t
2
MC Pulse Width High
180
MC
cycles
t
3
MC H-L to Active State
180
MC
cycles
t
PZXclk
Enable Time - Clock Start
RGB Mode
CLK to PDout*
Figure 4
7
PCLK
cycles
MPL POWER OFF TIMING
t
PAZ
Disable Time to Power
Down
(Note 8)
2ms
t
PXZclk
Disable Time - Clock Stop
PCLK to PD
OUT*
Figure 3
7
PCLK
cycles
www.national.com
5


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