TDA8358 datasheet(8/20 Pages) PHILIPS

Numer części	TDA8358

Szczegółowy opis	Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier

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Producent	PHILIPS [NXP Semiconductors]

Strona internetowa	http://www.nxp.com

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8 / 20 page

1999 Dec 22

8

Philips Semiconductors

Product speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS with east-west ampliﬁer

TDA8358J

Notes

1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and VFB at the first part of the flyback.

2. Allowable input range for both inputs: VI(bias) +Vi(dif)(peak) < 1600 mV and VI(bias) − Vi(dif)(peak) > 100 mV.

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and

between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and

between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time

parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists

of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,

where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum,

maximum and average voltages respectively. The linearity errors are defined as:

a)

(adjacent blocks)

b)

(non adjacent blocks)

Flyback switch

Io(peak)

maximum (peak) output current

t

≤ 1.5 ms

−−±1.8

A

Vloss(FB)

voltage loss at ﬂyback

note 11

Io = 1.1 A

−

7.5

8.5

V

Io = 1.6 A

−

89V

Guard circuit

VO(grd)

guard output voltage

IO(grd) = 100 µA

567V

VO(grd)(max) allowable guard voltage

maximum leakage current

IL(max) =10 µA

−−

18

V

IO(grd)

output current

VO(grd) = 0 V; not active

−−

10

µA

VO(grd) = 4.5 V; active

1

−

2.5

mA

East-west ampliﬁer

Vo

output voltage

at pin OUTEW

−−

68

V

Vloss

voltage loss

Io = 750 mA; note 12

−−

5V

VI(bias)

input bias voltage

2

2.5

3.2

V

II(bias)

input bias current

into pin INEW; note 13

Io = 100 mA

−

2.5

−µA

Io = 500 mA

−

11.5

−µA

Gv(ol)

open-loop voltage gain

−−

30

dB

THD

harmonic distortion

−

0.5

1

%

f−3dB(h)

high

−3 dB cut-off frequency

−−

1

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

LE

V

k

V

k1

+

–

V

avg

--------------------------

100%

×

=

LE

V

max

V

min

–

V

avg

-------------------------------

100%

×

=

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