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TDA8505 Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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TDA8505 Arkusz danych(HTML) 9 Page - NXP Semiconductors |
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9 / 32 page  July 1994 9 Philips Semiconductors Preliminary specification SECAM encoder TDA8505 CHROMINANCE BLANKING The chrominance signal is blanked by the internally generated chrominance blanking pulse. The output of this blanking stage is connected to the chrominance and CVBS output circuits. Y+SYNC, CVBS, AND CHROMA OUTPUTS The Y output signal of the matrix is added to the composite sync signal of the sync separator. The output of this adder at pin 25 is connected to the input of an external delay line which is necessary for correct timing of the Y+SYNC signal corresponding with the chrominance signal. The signal amplitude at pin 25 is 2 V (peak-to-peak value) nominal, so at the output of the delay line Y+SYNC is 1 V (peak-to-peak value). The delay line has to be DC-coupled between pins 25 and 23 to ensure the required DC level at pin 23. The output resistor of the delay line has to be connected to pin 17 where (Vref = 2.5 V). The output of the delay line is connected to pin 23 which is the input of a buffer operational amplifier. The output of the buffer operational amplifier is connected to pin 22 and to the CVBS adder stage via an internal resistor of 2 k Ω. An external notch filter can be connected to pin 22. The CVBS signal amplitude output at pin 21 is 2 V (peak-to-peak value) nominal. An external emitter follower is used to provide a 75 Ω output load. The amplitude of the chrominance output signal which is connected to pin 18 corresponds with the Y+SYNC signal at the output of the delay line. Modulator control circuit The modulator control circuit has two tuning modes which are controlled by the input at pin 26: • Tuning by line frequency • Tuning by crystal or external signal source. TUNING BY LINE FREQUENCY Two reference voltage controlled oscillators (VCOs) are integrated, the 4.4 MHz VCO with an internal capacitor and the 4.25 MHz VCO with an external capacitor at pin 27. A PLL loop with divider circuits directly couples the frequencies of the two VCOs with the line frequency of the sync separator sync signal. The loop filter for the 4.40625 MHz reference is at pin 24 and the loop filter for the 4.250 MHz reference is at pin 31. The outputs of the 272 divider are also used for pulse shaping. Within the vertical blanking period, another two Phase Locked Loops (PLLs) synchronizes the FM modulator during two lines with the 4.406 MHz reference VCO and during the following 2 lines with the 4.250 MHz reference VCO. The loop filters are connected to pins 13 and 15 respectively. It is necessary to use low-leakage capacitors for these loop filters. TUNING BY CRYSTAL OR EXTERNAL SIGNAL SOURCE When the frequency of the sync pulse at pin 29 is not stable or is incorrect it is possible to tune the FM modulator using an external 4.250 MHz crystal connected to pin 27. The 4.25 MHz loop at pin 31 has to be connected to pin 17 (Vref). A stable line frequency reference is generated by the 272 divider circuit which is used for the 4.406 MHz reference loop. An external signal source, instead of a crystal, can be connected at pin 27 via a capacitor in series with a resistor. The minimum AC current of 50 µA is determined by the resistor values (Rint +Rext) and the output voltage of the signal source (see Fig.7). When crystal tuning is used no vertical identification is possible. Crystal tuning is recommended for VTR signals. handbook, halfpage MSA732 - 1 1 nF R ext I 50 A µ signal source 27 R int 800 Ω OSCILLATOR TDA8505 V (p-p) Fig.7 Tuning circuit for external signal source. |
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