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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TDA8755T Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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TDA8755T Arkusz danych(HTML) 7 Page - NXP Semiconductors |
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7 / 20 page  1995 Mar 09 7 Philips Semiconductors Product specification YUV 8-bit video low-power analog-to-digital interface TDA8755 INU AND INV (PINS 7 AND 9) VI(p-p) input voltage, full range (peak-to-peak value) fi = 1.5 MHz 0.93 1.03 1.13 V ZI input impedance fi = 2 MHz − 30 − k Ω CI input capacitance fi = 2 MHz − 1 − pF INPUTS ISOLATION αct crosstalk between Y, U and V −−55 −50 dB Outputs SDN (PIN 8) Vref reference voltage − 3.32 − V VREG line regulation 4.75 V ≤ VCCA ≤ 5.25 V − 4.0 − mV IL load current −2 −− mA DIGITAL OUTPUTS D0 TO D7 AND D’0 TO D’3 (PINS 24 TO 31 AND 19 TO 22) VOL LOW level output voltage IO = 0.4 mA 0 − 0.4 V IO = 1.5 mA 0 − 0.5 V VOH HIGH level output voltage IO = −0.4 mA 2.4 − VCCD V IOZ output current in 3-state mode 0.4 V < VO <VCCD −20 − +20 µA Switching characteristics fclk(max) maximum clock frequency 20 −− MHz fclk(min) minimum clock frequency −− 2.0 MHz tCPH clock pulse width HIGH 20 −− ns tCPL clock pulse width LOW 20 −− ns Analog signal processing (fclk = 20 MHz; 50% clock duty factor) Gdiff differential gain note 1; see Fig.8 − 2 − % ϕ diff differential phase note 1; see Fig.8 − 3 − deg f1 fundamental harmonics (full-scale) note 2 −− 0dB fall harmonics (full-scale), all components note 2; see Fig.10 −−54 − dB SVRR1 supply voltage ripple rejection 1 note 3 −−40 − dB SVRR2 supply voltage ripple rejection 2 note 3 − 1.0 − %/V Transfer function (50% clock duty factor) INL DC integral non-linearity fclk = 2 MHz −±0.4 ±1.0 LSB DNL DC differential non-linearity fclk = 2 MHz −±0.3 ±0.5 LSB AILE AC integral non-linearity note 4 −±1.0 ±2.0 LSB EB effective bits note 5; Fig.10 − 7.1 − bits SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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