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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TDA9160 Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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TDA9160 Arkusz danych(HTML) 7 Page - NXP Semiconductors |
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7 / 27 page  December 1991 7 Philips Semiconductors Preliminary specification PAL/NTSC/SECAM decoder/sync processor TDA9160 right-hand side (50 Hz) of the state diagram. Figure 6 illustrates the state diagram of the 'norm' counter which is an up/down counter that counts up if it finds a vertical sync pulse within the selected window. In the NEAR-NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR-NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. If no vertical sync pulse is found in the selected window this will always result in a down pulse for the 'norm' counter. Figure 7 illustrates the timing of the display sandcastle (DSC) and the reset pulse of the vertical sawtooth with respect to the input signal I2C-bus protocol If the TXT output is connected to the positive supply the address will change from 8A to 8E. Valid subaddresses = 00 to 0F Auto-increment mode available for subaddresses. Subaddress 00 must always be sent before subaddress 01 in order to protect the horizontal output transistor. Table 1 Slave address (8A) Table 2 Inputs Table 3 Outputs A6 A5 A4 A3 A2 A1 A0 R/W 1000 1X 1X SUBADDRESS MSB LSB 00 INA INB INC IND FOA FOB XA XB 01 FORF FORS DL STB POC FM SAF FRQF 02 −− HU5 HU4 HU3 HU2 HU1 HU0 03 −− HS5 HS4 HS3 HS2 HS1 HS0 04 −− EW5 EW4 EW3 EW2 EW1 EW0 05 −− PW5 PW4 PW3 PW2 PW1 PW0 06 −− CP5 CP4 CP3 CP2 CP1 CP0 07 −− TC5 TC4 TC3 TC2 TC1 TC0 08 −− VS5 CS4 VS3 VS2 VS1 VS0 09 −− VA5VA4 VA3VA2 VA1VA0 0A −− SC5 SC4 SC3 SC2 SC1 SC0 0B SBL − VSH5 VSH4 VSH3 VSH2 VSH1 VSH0 ADDRESS POR FSI STS SL PROT SAK SBK FRQ |
Podobny numer części - TDA9160 |
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Podobny opis - TDA9160 |
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