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TDA9874A Arkusz danych(PDF) 11 Page - NXP Semiconductors |
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TDA9874A Arkusz danych(HTML) 11 Page - NXP Semiconductors |
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11 / 68 page  1999 Dec 03 11 Philips Semiconductors Preliminary specification Digital TV sound demodulator/decoder TDA9874A 6.1.10 CRYSTAL OSCILLATOR The digital controlled crystal oscillator (DCXO) is fully integrated. Only an external 24.576 MHz crystal is required. 6.1.11 TEST PINS All test pins are active HIGH. In normal operation of the device they can be left open-circuit, as they have internal pull-down resistors. Test functions are for manufacturing tests only and are not available to customers. 6.1.12 POWER FAIL DETECTOR The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the power failure register bit PFR in subaddress 0 (see Section 10.4.1), will be set to HIGH. The CLRPFR bit, slave register subaddress 1 (see Section 10.3.3), resets the Power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9874A has to be performed to ensure reliable operation. 6.1.13 POWER-ON RESET The reset is active LOW. In order to perform a reset at power-up, a simple RC circuit may be used which consists of an integrated passive pull-up resistor and an external capacitor connected to ground. The pull-up resistor has a nominal value of 50 k Ω, which can easily be measured between pins CRESET and VDDD3. Before the supply voltage has reached a certain minimum level, the state of the circuit is completely undefined and remains in this undefined state until a reset is applied. The reset is guaranteed to be active when: • The power supply is within the specified limits (4.5 to 5.5 V) • The crystal oscillator (DCXO) is functioning • The voltage at pin CRESET is below 0.3VDDD (1.5 V if VDDD = 5.0 V, typically below 1.8 V). The required capacitor value depends on the gradient of the rising power supply voltage. The time constant of the RC circuit should be clearly larger than the rise time of the power supply [to make sure that the reset condition is always satisfied (see Fig.4)], even when considering tolerance spreading. To avoid problems with a too slow discharging of the capacitor at power-down, it may be helpful to add a diode from the CRESET pin to VDDD. It should be noted that the internal ESD protection diode does not help here as it only conducts at higher voltages. Under difficult power supply conditions (e.g. very slow or non-monotonic ramp-up), it is recommended to drive the reset line from a microcontroller port or the like. 6.2 Description of the DSP 6.2.1 LEVEL SCALING All input channels to the digital crossbar switch are equipped with a level adjustment facility to change the signal level in a range of ±15 dB. Adjusting the signal level is intended to compensate for the different modulation parameters of the various TV standards. Under nominal conditions it is recommended to scale all input channels to be 15 dB below full-scale [ −15 dB (FS)]. This will create sufficient headroom to cope with overmodulation and avoids changes of the volume impression when switching from FM to NICAM or vice versa. 6.2.2 NICAM PATH The NICAM path has a switchable J17 de-emphasis. 6.2.3 NICAM AUTO-MUTE If NICAM is received, the auto-mute is enabled and the signal quality becomes poor. The digital crossbar switches automatically to FM, channel 1 or the analog mono input, as selected by bit AMSEL. This automatic switching depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus. handbook, halfpage MHB587 reset active guaranteed 1.5 5 V t VCRESET < 0.3VDDD VDDD > 4.5 V Fig.4 Reset at power-on. |
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