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CDCE937 Arkusz danych(PDF) 11 Page - Texas Instruments |
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CDCE937 Arkusz danych(HTML) 11 Page - Texas Instruments |
11 / 21 page www.ti.com DATA PROTOCOL COMMAND CODE DEFINITION Generic Programming Sequence 1 7 1 1 8 1 1 S Slave Address A DataByte A P MSB LSB MSB LSB S StartCondition Sr RepeatedStartCondition 1=Read(Rd)FromCDCE9xxDevice;0=Write(Wr)toCDCE9xxx A Acknowledge(ACK=0andNACK=1) P StopCondition Master-to-Slave Transmission Slave-to-Master Transmission R/W R/W CDCE913 CDCEL913 SCAS849A – JUNE 2007 – REVISED AUGUST 2007 The device supports Byte Write and Byte Read and Block Write and Block Read operations. For Byte Write/Read operations, the system controller can individually access addressed bytes. For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction, all bytes defined in the Byte Count must be readout to correctly finish the read cycle. Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to each transferred byte regardless of whether this is a Byte Write or a Block Write sequence. If the EEPROM Write Cycle is initiated, the internal SDA registers are written into the EEPROM. During this Write Cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by EEPIP, byte 01h–bit 6. The offset of the indexed byte is encoded in the command code, as described in Table 5. Table 5. Slave Receiver Address (7 Bits) DEVICE A6 A5 A4 A3 A2 A1(1) A0(1) R/W CDCE913/CDCEL913 1 1 0 0 1 0 1 1/0 CDCE925/CDCEL925 1 1 0 0 1 0 0 1/0 CDCE937/CDCEL937 1 1 0 1 1 0 1 1/0 CDCE949/CDCEL949 1 1 0 1 1 0 0 1/0 (1) Address bits A0 and A1 are programmable via the SDA/SCL bus (byte 01, bit [1:0]. This allows addressing up to 4 devices connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation. Table 6. Command Code Definition BIT DESCRIPTION 0 = Block Read or Block Write operation 7 1 = Byte Read or Byte Write operation (6:0) Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation. Figure 7. Generic Programming Sequence Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): CDCE913 CDCEL913 |
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