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TSA5059 Arkusz danych(PDF) 9 Page - NXP Semiconductors |
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TSA5059 Arkusz danych(HTML) 9 Page - NXP Semiconductors |
9 / 24 page 1999 Oct 05 9 Philips Semiconductors Preliminary specification 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer TSA5059 Reference divider ratio The reference divider ratio is set by 4 bits in the WRITE mode, giving 16 different ratios which allow to adjust the comparison frequency to different values, depending on the compromise which has to be found between step size and phase noise. Table 8 shows the different dividing ratios and the corresponding comparison frequencies and step size, assuming the device is provided with a 4 MHz signal at pin XTAL. The dividing ratio of 24 is implemented to fulfil the UK-DTT recommendation regarding offset frequency of 1 ⁄6 MHz. Table 8 Reference dividing ratios Note 1. Only valid when the IC is used with a 4 MHz crystal. Charge pump current The charge pump current can be chosen from 4 different values depending on the value of bits C1 and C0 in the I2C-bus byte 4, according to Table 9. Table 9 Charge pump current R3 R2 R1 R0 RATIO COMPARISON FREQUENCY(1) STEP BIT PE = 0(1) BIT PE = 1(1) 0000 2 2 MHz 2 MHz 4 MHz 0001 4 1 MHz 1 MHz 2 MHz 0010 8 500 kHz 500 kHz 1 MHz 0011 16 250 kHz 250 kHz 500 kHz 0100 32 125 kHz 125 kHz 250 kHz 0101 64 62.5 kHz 62.5 kHz 125 kHz 0110 128 31.25 kHz 31.25 kHz 62.5 kHz 0111 256 15.625 kHz 15.625 kHz 31.25 kHz 1000 24 166.67 kHz 166.67 kHz 333.33 kHz 1001 5 800 kHz 800 kHz 1.6 MHz 1010 10 400 kHz 400 kHz 800 kHz 1011 20 200 kHz 200 kHz 400 kHz 1100 40 100 kHz 100 kHz 200 kHz 1101 80 50 kHz 50 kHz 100 kHz 1110 160 25 kHz 25 kHz 50 kHz 1111 320 12.5 kHz 12.5 kHz 25 kHz C1 C0 Icp (µA) (absolute value) MIN. TYP. MAX. 0 0 100 135 170 0 1 210 280 350 1 0 450 600 750 1 1 920 1230 1560 |
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