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CS42432-DMZR Arkusz danych(PDF) 30 Page - Cirrus Logic |
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CS42432-DMZR Arkusz danych(HTML) 30 Page - Cirrus Logic |
30 / 59 page 30 DS673F1 CS42432 5.3.3 Digital Volume Control 5.3.3.1 Hardware Mode DAC Volume Control and Mute are not accessible in Hardware Mode. 5.3.3.2 Software Mode Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to -127.5 dB attenuation with 0.5 dB resolution. See “AOUTX Volume Control (Addresses 08h-0D)” on page 45. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate con- trolled by the SZC[1:0] bits in the Digital Volume Control register. See “Transition Control (Address 06h)” on page 43. Each output can be independently muted via mute control bits in the register “DAC Channel Mute (Ad- dress 07h)” on page 44. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits. 5.3.4 De-Emphasis Filter The CS42432 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re- sponse is shown in Figure 12. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode. Please see “DAC De-Emphasis Control (DAC_DEM)” on page 42 for de-emphasis control. AOUTx+ AOUTx- Full-Scale Differential Output Level = (AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS 4.125 V 2.5 V 0.875 V 5.0 V 4.125 V 2.5 V 0.875 V VA Figure 11. Full-Scale Output |
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