AD9627BCPZ-80 datasheet(7/40 Pages) AD

Numer części	AD9627BCPZ-80

Szczegółowy opis	12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

Download	40 Pages

Scroll/Zoom	100%

Producent	AD [Analog Devices]

Strona internetowa	http://www.analog.com

Logo

7 / 40 page

Preliminary Technical Data

AD9627

Rev. PrA | Page 7 of 40

SWITCHING SPECIFICATIONS

Table 4.

AD9627BCPZ-80

AD9627BCPZ-105

AD9627BCPZ-125

AD9627BCPZ-150

Unit

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Full

80

105

125

150

MSPS

Minimum Conversion Rate

Full

10

MSPS

CLK Period(tCLK)

Full

12.5

9.5

8

6.66

ns

CLK Pulse Width High1(tCLKH)

Full

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

ns

CLK Pulse Width Low1 (tCLKL)

Full

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

ns

CLK Pulse Width High2(tCLKH)

Full

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

ns

CLK Pulse Width Low2(tCLKL)

Full

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

TBD

tCLK/2

ns

DATA OUTPUT PARAMETERS

Data Propagation Delay

(tPD)3

Full

TBD

ns

DCO Propagation Delay

(tDCO)

Full

TBD

ns

Setup Time (tS)

Full

8.5

ns

Hold Time (tH)

Full

8.5

ns

Pipeline Delay (Latency)

Full

12

Cycles

Aperture Delay (tA)

Full

TBD

ns

Aperture Uncertainty (Jitter,

tJ)

Full

0.1

ps rms

Wake-Up Time4

Full

TBD

ms

OUT-OF-RANGE RECOVERY

TIME

Full

TBD

Parameter (Conditions)

Min

Typ

Max

Unit

RESET TIMING REQUIREMENTS

tRESL

RESET Width Low

TBD

ns

SYNC TIMING REQUIREMENTS

tSS

SYNC to

↑CLK Setup Time

TBD

ns

tHS

SYNCto

↑CLK Hold Time

TBD

ns

SPI TIMING REQUIREMENTS

tDS

Set-up time between the data and the rising edge of SCLK

5

ns

tDH

Hold time between the data and the rising edge of SCLK

5

ns

tCLK

Period of the SCLK

40

ns

tS

Set-up time between CSB and SCLK

TBD

ns

tH

Hold time between CSB and SCLK

TBD

ns

tHI

Minimum period that SCLK should be in a logic high state

TBD

ns

tLO

Minimum period that SCLK should be in a logic low state

TBD

ns

1 With duty cycle stabilizer (DCS) enabled.

2 With duty cycle stabilizer (DCS) disabled.

3 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

4 Wake-up time is dependant on the value of the decoupling capacitors.

Podobny numer części - AD9627BCPZ-80

Producent	Numer części	Arkusz danych	Szczegółowy opis
Analog Devices	AD9627	2Mb / 76P	12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9627	2Mb / 77P	1.8 V Dual Analog-to-Digital Converter
	AD9627-11	4Mb / 72P	11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9627-125EBZ	2Mb / 77P	1.8 V Dual Analog-to-Digital Converter
	AD9627-150EBZ	2Mb / 77P	1.8 V Dual Analog-to-Digital Converter

More results

Podobny opis - AD9627BCPZ-80

Producent	Numer części	Arkusz danych	Szczegółowy opis
Analog Devices	AD9627ABCPZ-125	2Mb / 76P	12-Bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9233	1Mb / 44P	12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter REV. A
	AD9233	1Mb / 44P	12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter REV. A
	AD9640	931Kb / 41P	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter Rev. PrD
	AD9640ABCPZ-80	1Mb / 52P	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9640	1Mb / 52P	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9640ABCPZ-105	1Mb / 52P	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. B
	AD9628	1,023Kb / 44P	12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter REV. 0
	AD9628	1Mb / 42P	12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
	AD9265	1Mb / 45P	16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

More results

AD9627BCPZ-80 Arkusz danych(PDF) 7 Page - Analog Devices

AD9627BCPZ-80 Arkusz danych(HTML) 7 Page - Analog Devices

Podobny numer części - AD9627BCPZ-80

Podobny opis - AD9627BCPZ-80

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Arkusz danych Pobierz

Link URL