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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADAU1401YSTZ Arkusz danych(PDF) 6 Page - Analog Devices |
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ADAU1401YSTZ Arkusz danych(HTML) 6 Page - Analog Devices |
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6 / 52 page  ADAU1401 Rev. 0 | Page 6 of 52 DIGITAL TIMING SPECIFICATIONS Table 8. Digital Timing1 Limit Parameter tMIN tMAX Unit Description MASTER CLOCK tMP 36 244 ns MCLKI period, 512 × fS mode. tMP 48 366 ns MCLKI period, 384 × fS mode. tMP 73 488 ns MCLKI period, 256 × fS mode. tMP 291 1953 ns MCLKI period, 64 × fS mode. SERIAL PORT tBIL 40 ns INPUT_BCLK low pulse width. tBIH 40 ns INPUT_BCLK high pulse width. tLIS 10 ns INPUT_LRCLK setup. Time to INPUT_BCLK rising. tLIH 10 ns INPUT_LRCLK hold. Time from INPUT_BCLK rising. tSIS 10 ns SDATA_INx setup. Time to INPUT_BCLK rising. tSIH 10 ns SDATA_INx hold. Time from INPUT_BCLK rising. tLOS 10 ns OUTPUT_LRCLK setup in slave mode. tLOH 10 ns OUTPUT_LRCLK hold in slave mode. tTS 5 ns OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew. tSODS 40 ns SDATA_OUTx delay in slave mode. Time from OUTPUT_BCLK falling. tSODM 40 ns SDATA_OUTx delay in master mode. Time from OUTPUT_BCLK falling. SPI PORT fCCLK 6.25 MHz CCLK frequency. tCCPL 80 ns CCLK pulse width low. tCCPH 80 ns CCLK pulse width high. tCLS 0 ns CLATCH setup. Time to CCLK rising. tCLH 100 ns CLATCH hold. Time from CCLK rising. tCLPH 80 ns CLATCH pulse width high. tCDS 0 ns CDATA setup. Time to CCLK rising. tCDH 80 ns CDATA hold. Time from CCLK rising. tCOD 101 ns COUT delay. Time from CCLK falling. I2C PORT fSCL 400 kHz SCL frequency. tSCLH 0.6 μs SCL high. tSCLL 1.3 μs SCL low. tSCS 0.6 μs Setup time, relevant for repeated start condition. tSCH 0.6 μs Hold time. After this period, the first clock is generated. tDS 100 ns Data setup time. tSCR 300 ns SCL rise time. tSCF 300 ns SCL fall time. tSDR 300 ns SDA rise time. tSDF 300 ns SDA fall time. tBFT 0.6 Bus-free time. Time between stop and start. MULTIPURPOSE PINS AND RESET tGRT 50 ns GPIO rise time. tGFT 50 ns GPIO fall time. tGIL 1.5 × 1/fS μs GPIO input latency. Time until high/low value is read by core. tRLPW 20 ns RESET low pulse width. 1 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 67). |
Podobny numer części - ADAU1401YSTZ |
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Podobny opis - ADAU1401YSTZ |
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