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CY24488
Document #: 001-09608 Rev. *A
Page 6 of 15
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Table 6. CLKE Output Frequencies (Ethernet, Video, PCI, Processor)
Frequency (MHz)
Application
Frequency
Error
Register Address
13H
14H
15H
53H[2]
CLKE off and PLL off (default)
–
–
–
–
00
3E
CLKE off
–
–
–
–
–
3E
13.5
Video
0 ppm
00
05
26
8E
27 (reference)
Video
0 ppm
–
–
02
6E
54
Video
0 ppm
00
06
24
2E
81
Video
0 ppm
00
07
24
DE
108
Video
0 ppm
00
06
24
5E
20
Processor
0 ppm
07
26
24
9E
25
Ethernet
0 ppm
07
17
30
AE
30
Processor
0 ppm
01
08
28
AE
33.333333
PCI
0 ppm
19
62
30
AE
40
Processor
0 ppm
07
26
30
AE
50
Processor
0 ppm
19
62
30
2E
60
Processor
0 ppm
01
08
28
DE
66.666666
PCI
0 ppm
19
62
30
DE
80
Processor
0 ppm
07
26
30
DE
100
Processor
0 ppm
19
62
30
5E
Table 7. CLKF Output Clock
Frequency (MHz)
Address 55H
Data value (hex)
CLKF off (default)
0C
27 MHz reference
18
Copy of CLKC
copy of data from Table 4 address 48H
Copy of CLKD
copy of data from Table 5 address 50H
Copy of CLKE
copy of data from Table 6 address 53H, divided by 4[3]
Table 8. CLKG Output Clock (Default = Reference out)
Frequency (MHz)
Address 57H
bits [7:6]
bits [5:0]
CLKG off
10
001100
27 MHz reference (default)
dr
i
vest
r
engt
h(
def
aul
t
=10)–seeTable 10
011000
Copy of CLKC
dr
i
vest
r
engt
h(
def
aul
t
=10)–seeTable 10
bi
t
s[
5:
0]ofaddr
ess48H–seeTable 4
Copy of CLKD
dr
i
vest
r
engt
h(
def
aul
t
=10)–seeTable 10
bi
t
s[
5:
0]ofaddr
ess50H–seeTable 5
Copy of CLKE
dr
i
vest
r
engt
h(
def
aul
t
=10)–seeTable 10
bi
t
s[
7:
2]ofaddr
ess53H–seeTable 6
Notes
2.
Bi
t
s[
1:
0]cont
r
olCLKDdr
i
vest
r
engt
h.Theval
uesgi
veni
nt
hi
st
abl
ecor
r
espondt
oadr
i
vest
r
engt
hset
t
i
ngof‘
10’
.SeeTable 9 and Table 10.
3.
Bi
t
s[
7:
6]ofaddr
ess55Har
edon’
tcar
e.Di
vi
di
ngby4i
sequi
val
entt
or
i
ghtshi
f
t
i
ngby2bi
t
s.
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