Si5365

8

Preliminary Rev. 0.34

3RST

ILVCMOS

External Reset.

Active low input that performs external hardware reset of device. Resets

all internal logic to a known state and forces the device registers to their

default value. Clock outputs are tristated during reset. After rising edge

of RST signal, the device will perform an internal self-calibration.

This pin has a weak pull-up.

4

FRQTBL

I

3-Level

Frequency Table Select.

This pin selects SONET/SDH, datacom, or SONET/SDH to datacom fre-

quency translation table.

L = SONET/SDH.

M= Datacom.

H = SONET/SDH to Datacom.

This pin has a weak pull-down.

5, 6, 15,

27, 32, 42,

62, 63, 76,

79, 81, 84,

86, 89, 91,

94, 96, 99,

100

Supply

The device operates from a 1.8 or 2.5 V supply. Bypass capacitors

Pins

Bypass Cap

5, 6

0.1 µF

15

0.1 µF

27

0.1 µF

62, 63

0.1 µF

76, 79

1.0 µF

81, 84

0.1 µF

86, 89

0.1 µF

91, 94

0.1 µF

96, 99, 100

0.1 µF

7, 8, 14,

16, 18, 19,

26, 28, 31,

33, 36, 38,

41, 43, 46,

51, 56, 64,

65

GND

GND

Supply

Ground.

These pins must be connected to system ground. Minimize the ground

path impedance for optimal performance.

9C1B

O

LVCMOS

CKIN1 Invalid Indicator.

This pin is an active high alarm output associated with CKIN1. Once trig-

gered, the alarm will remain high until CKIN1 is validated.

0 = No alarm on CKIN1.

1 = Alarm on CKIN1.

10

C2B

O

LVCMOS

CKIN2 Invalid Indicator.

This pin is an active high alarm output associated with CKIN2. Once trig-

gered, the alarm will remain high until CKIN2 is validated.

0 = No alarm on CKIN2.

1 = Alarm on CKIN2.

11

C3B

O

LVCMOS

CKIN3 Invalid Indicator.

This pin is an active high alarm output associated with CKIN3.

0 = No alarm on CKIN3.

1 = Alarm on CKIN3.

Table 3. Si5365 Pin Descriptions (Continued)

Pin #

Pin Name I/O Signal Level

Description