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ADS5232

SBAS294A – JUNE 2004 – REVISED MARCH 2006

ELECTRICAL CHARACTERISTICS (continued)

T

AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I

otherwise noted.

ADS5232

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT

Differential Input Capacitance

3

pF

Analog Input Common-Mode Range

V

Differential Input Voltage Range

Internal Reference

2.02

External Reference

3

CLK Cycles

–3dBFS Input, 25

Ω Series

Input Bandwidth

300

MHz

Resistance

DIGITAL DATA INPUTS

Logic Family

+3V CMOS Compatible

2.2

V

0.6

V

3

pF

DIGITAL OUTPUTS

Data Format

Logic Family

CMOS

Logic Coding

Straight Offset Binary or BTC

+0.4

V

+2.4

V

3-State Enable Time

2

Clocks

3-State Disable Time

2

Clocks

Output Capacitance

3

pF

SERIAL INTERFACE

SCLK Serial Clock Input Frequency

20

MHz

CONVERSION CHARACTERISTICS

Sample Rate

20

65

MSPS

Data Latency

6

CLK Cycles

(8)

A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the

full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the

ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value

when the pulse is switched from ON (high) to OFF (low).

(9)

Option for Binary Two’s Complement Output.

5

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