www.lansdale.com

Page 10 of 16

Issue A

ML13155

LANSDALE Semiconductor, Inc.

Block Diagram of 70 MHz Video Receiver Application Circuit

Input

– 45 dBm

– 70 dBm

– 72 dBm

– 32 dBm

– 47 dBm

Minimum Input to Acquire

Level:

1.26 mVrms

71

µVrms

57

µVrms

57

µVrms

1.0 mVrms

Limiting in ML13155

ML13155

7

10

1

16

1

16

ML13155

40 dB Gain

–15 dB

(Attenuator)

40 dB Gain

1:4

Transformer

2.0 dB

(Insertion Loss)

– 25 dB

(Insertion Loss)

Saw

Filter

IF

Input

DC BIASING CONSIDERATIONS

The DC biasing scheme utilizes two VCC connections (Pins 3 and

6) and two VEE connections (Pins 14 and 11). VEE1 (Pin 14) is

connected internally to the IF and RSSI circuits’ negative supply bus

while the VEE2 (Pin 11) is connected internally to the quadrature

detector’s negative bus. Under positive ground operation, this

unique configuration offers the ability to bias the RSSI and IF sepa-

rately from the quadrature detector. When two ICs are cascaded as

shown in the 70 MHz application circuit and provided by the PCB

(see Figures 17 and 18), the first ML13155 is used without biasing

its quadrature detector, thereby saving approximately 3.0 mA. A

total current of 7.0 mA is used to fully bias each IC, thus the total

current in the application circuit is approximately 11 mA. Both VCC

pins are biased by the same supply. VCC1 (Pin 3) is connected inter-

nally to the positive bus of the first half of the IF limiting amplifier,

while VCC2 is internally connected to the positive bus of the RSSI,

the quadrature detector circuit, and the second half of the IF limiting

amplifier (see Figure 15). This distribution of the VCC enhances the

stability of the IC.

RSSI CIRCUITRY

The RSSI circuitry provides typically 35 dB of linear dynamic range

and its output voltage swing is adjusted by selection of the resistor

from Pin 12 to VEE. The RSSI slope is typically 2.1 µA/dB; thus,

for a dynamic range of 35 dB, the current output is approximately

74

µA. A 47 k resistor will yield an RSSI output voltage swing of

3.5 Vdc. The RSSI buffer output at Pin 13 is an emitter–follower

and needs an external emitter resistor of 10 k to VEE.

In a cascaded configuration (see circuit application in Figure 16),

only one of the RSSI Buffer outputs (Pin 13) is used; the RSSI out-

puts (Pin 12 of each IC) are tied together and the one closest to the

VEE supply trace is decoupled to VCC ground. The two pins are

connected to VEE through a 47 k resistor. This resistor sources a

RSSI current which is proportional to the signal level at the IF input;

typically 1.0 mVms (–47 dBm) is required to place the ML13155

into limiting. The measured RSSI output voltage response of the

application circuit is shown in Figure 12. Since the RSSI current

output is dependent upon the input signal level at the IF input, a

careful accounting of filter losses, matching and other losses and

gains must be made in the entire receiver system. In the block dia-

gram of the application circuit shown below, an accounting of the

signal levels at points throughout the system shows how the RSSI

response in Figure 12 is justified.

CASCADING STAGES

The limiting IF output is pinned–out differentially, cascading is easi-

ly achieved by AC coupling stage to stage. In the evaluation PCB,

AC coupling is shown, however interstage filtering may be desirable

in some application. In which case, the S–parameters provide a

means to implement a low loss interstage match and better receiver

sensitivity.

Where a linear response of the RSSI output is desired when cascad-

ing the ICs, it is necessary to provide at least 10 dB of interstage

loss. Figure 12 shows the RSSI response with and without interstage

loss. A 15 dB resistive attenuator is an inexpensive way to linearize

the RSSI response. This has its drawbacks since it is a wideband

noise source that is dependent upon the source and load impedance

and the amount of attenuation that it provides. A better, although

more costly, solution would be a bandpass filter designed to the

desired center frequency and bandpass response while carefully

selecting the insertion loss. A network topology shown below may

be used to provide a bandpass response with the desired insertion loss.

1.0n

1

16

7

10

0.22

µ

1.0n

Network Topology