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FEATURES

TSB83AA22C

SLLS851 – JUNE 2007

TSB83AA22C IEEE Std 1394b-2002 Phy and OHCI Link Device

• Fully Supports Provisions of IEEE Std

• Software Device Reset (SWR)

1394b-2002 Revision 1.33+ at 1-Gigabit

• Fail-Safe Circuitry Senses Sudden Loss of

Signaling Rates

Power to the Device and Disables the Ports

• Fully Supports Provisions of IEEE Std

Ensure That the TSB83AA22C Does Not Load

1394a-2000 and IEEE Std 1394-1995 Standards

the TPBIAS of Any Connected Device and

for High-Performance Serial Bus

Blocks any Leakage From the Port Back to

Power Plane

• Fully Interoperable With Firewire™, i.LINK™,

and SB1394 Implementations of IEEE Std 1394

• IEEE Std 1394a-2000-Compliant

Common-Mode Noise Filter on Incoming Bias

• Provides Two Fully Backward-Compatible,

Detect Circuit to Filter Out Crosstalk Noise

IEEE Std 1394a-2000 Fully Compliant)

Bilingual IEEE Std 1394b-2002 Cable Ports at

• Port Programmable to Force IEEE Std

up to 800 Megabits per Second (Mbps)

1394a-2000 Mode to Allow Use of IEEE Std

1394a-2000 Connectors (IEEE Std 1394b-2002

• Full IEEE Std 1394a-2000 Support Includes:

Signaling Must Not Be Put Across IEEE Std

–

Connection Debounce

1394a-2000 Connectors or Cables)

–

Arbitrated Short Reset

• 3.3-V and 5-V PCI Signaling Environments

–

Multispeed Concatenation

• Serial-Bus Data Rates of 100 Mbps, 200 Mbps,

–

Arbitration Acceleration

400 Mbps, and 800 Mbps

–

Fly-By Concatenation

• Physical Write Posting of up to Three

–

Port Disable/Suspend/Resume

Outstanding Transactions

• Extended Resume Signaling for Compatibility

• Serial ROM or Boot ROM Interface Supports

With Legacy DV Devices

2-Wire Serial EEPROM Devices

• Power-Down Features to Conserve Energy in

• 33-MHz/32-Bit PCI Interface

Battery-Powered Applications

• Multifunction Terminal (MFUNC Terminal 1):

• Low-Power Sleep Mode

–

PCI_CLKRUN Protocol per the PCI Mobile

• Fully Compliant With Open Host Controller

Design Guide

Interface (OHCI) Requirements

–

General-Purpose I/O

• Cable Power Presence Monitoring

–

CYCLEIN/CYCLEOUT for External Cycle

• Cable Ports Monitor Line Conditions for

Timer Control for Customized

Active Connection to Remote Node

Synchronization

• Register Bits Give Software Control of

• PCI Burst Transfers and Deep FIFOs to

Contender Bit, Power-Class Bits, Link Active

Tolerate Large Host Latency:

Control Bit, and IEEE Std 1394a-2000 Features

–

Transmit FIFO—5K Asynchronous

• Interoperable With Other 1394 Physical Layers

–

Transmit FIFO—2K Isochronous

(Phy) Using 1.8-V, 3.3-V, and 5-V Supplies

–

Receive FIFO—2K Asynchronous

• Low-Jitter, External Crystal Oscillator

–

Receive FIFO—2K Isochronous

Provides Transmit and Receive Data at

• D0, D1, D2, and D3 Power States and PME

100/200/400/800 Mbps and Link-Layer

Events per the PCI Bus Power Management

Controller Clock at 49.152 MHz and

Interface Specification

98.304 MHz

• Programmable Asynchronous Transmit

• Separate Bias (TPBIAS) for Each Port

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Firewire is a trademark of Apple Computer, Inc.

i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.