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ADS8515IDBR Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS8515IDBR Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 22 page www.ti.com STARTING A CONVERSION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ADS8515 +5V + + + + Convert Pulse 40 ns Min 2.2 µF 0.1 µF 10 µF D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 2.2 µF BUSY R/C ADS8515 SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of the ADS8515 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until conversion n is completed and the internal output register has been updated. The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY states and Figure 21, Figure 22, and Figure 23 for the timing diagrams. CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical input is low at least 10 ns prior to the initiating input. To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The parallel output becomes active whenever R/C goes high. Refer to the Reading Data section. Table 1. Control Line Functions for Read and Convert CS R/C BUSY OPERATION 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion n. Databus remains in Hi-Z state. 0 ↓ 1 Initiates conversion n. Databus enters Hi-Z state. 0 1 ↑ Conversion n completed. Valid data from conversion n on the databus. ↓ 1 1 Enables databus with valid data from conversion n. ↓ 1 0 Enables databus with valid data from conversion –1(1). Conversion n in progress. 0 ↑ 0 Enables databus with valid data from conversion –1(1). Conversion n in progress. 0 0 ↑ New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C must be high when BUSY goes high. X X 0 Conversion n in progress. (1) See Figure 21 and Figure 22 for constraints on data valid from conversion n-1. Figure 19. Basic Operation Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS8515 |
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