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ADS8515IDBRG4 Arkusz danych(PDF) 3 Page - Texas Instruments |
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ADS8515IDBRG4 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 22 page www.ti.com ADS8515 SLAS460A – JUNE 2007 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8515I ADS8515IB PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Full-scale -0.5 0.5 -0.25 0.25 Int. Ref. %FSR error (3) (4) Full-scale error drift Int. Ref. ±7 ±7 ppm/ °C Full-scale -0.25 0.25 -0.1 0.1 Ext. 4.096-V Ref. %FSR error (3) (4) Full-scale error drift Ext. 4.096-V Ref. ±2 ±2 ppm/ °C Bipolar zero error (3) -4 4 -2 2 mV Bipolar zero error drift ±2 ±2 ppm/ °C Power supply sensitivity -8 8 -8 8 +4.75 V < VD < +5.25 V LSB (VDIG = VANA = VD) AC ACCURACY SFDR Spurious-free dynamic range fI = 20 kHz 95 102 97 102 dB (5) THD Total harmonic distortion fI = 20 kHz -100 -94 -100 -96 dB fI = 20 kHz 87 91 89 91 dB SINAD Signal-to-(noise+distortion) –60-dB Input 30 32 dB SNR Signal-to-noise ratio fI = 20 kHz 88 92 90 92 dB Full-power bandwidth (6) 500 500 kHz SAMPLING DYNAMICS Aperture delay 5 5 ns Transient response FS Step 2 2 µs Overvoltage recovery (7) 150 150 ns REFERENCE Internal reference voltage 4.076 4.096 4.116 4.076 4.096 4.116 V Internal reference source current (must 1 1 µA use external buffer) Internal reference drift 8 8 ppm/ °C External reference voltage range for 3.9 4.096 4.2 3.9 4.096 4.2 V specified linearity External reference current drain Ext. 4.096-V Ref. 100 100 µA DIGITAL INPUTS Logic levels VIL Low-level input voltage VDIG = 1.65 V – 5.25 V -0.3 0.8 -0.3 0.35*VDIG V VIH High-level input voltage VDIG = 1.65 V – 5.25 V 0.65*VDIG VDIG+0.3 V 0.65*VDIG VDIG+0.3 V V IIL Low-level input current VIL = 0 V ±10 ±10 µA IIH High-level input current VIH = 5 V ±10 ±10 µA DIGITAL OUTPUTS Data format (Parallel 16-bits) Data coding (Binary 2's complement) VOL Low-level output voltage ISINK = 1.6 mA 0.4 0.4 V VOH High-level output voltage ISOURCE = 500 µA 0.8 ×V DIG 0.8 ×V DIG V Hi-Z state, ±5 ±5 µA Leakage current VOUT = 0 V to VDIG Output capacitance Hi-Z state 15 15 pF DIGITAL TIMING Bus access timing 83 83 ns Bus relinquish timing 83 83 ns POWER SUPPLIES (3) As measured with fixed resistors shown in Figure 22. Adjustable to zero with external potentiometer. (4) Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10-V input. (6) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): ADS8515 |
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