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ADS1174IPAPT Arkusz danych(PDF) 7 Page - Texas Instruments

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Numer części ADS1174IPAPT
Szczegółowy opis  Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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ADS1174IPAPT Arkusz danych(HTML) 7 Page - Texas Instruments

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CLK
t
CPW
t
CLK
t
CPW
t
SD
t
S
t
DIST
t
DOHD
t
SPW
Bit15(MSB)
Bit14
Bit13
t
SPW
t
DOPD
t
CD
t
DS
t
MSBPD
t
DIHD
· · ·
t
CONV
DRDY
SCLK
DOUT
DIN
TIMING REQUIREMENTS: SPI FORMAT
ADS1174
ADS1178
SBAS373 – OCTOBER 2007
TIMING CHARACTERISTICS: SPI FORMAT
For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tCLK
CLK period (1/fCLK)
37
10,000
ns
tCPW
CLK positive or negative pulse width
15
ns
tCONV
Conversion period (1/fDATA)
(1)
256
2560
CLK periods
tCD
(2)
Falling edge of CLK to falling edge of DRDY
22
ns
tDS
(2)
Falling edge of DRDY to rising edge of first SCLK to retrieve data
1
CLK period
tMSBPD
DRDY falling edge to DOUT MSB valid (propagation delay)
12
ns
tSD
(2)
Falling edge of SCLK to rising edge of DRDY
18
ns
tS
(3)
SCLK period
tCLK
ns
tSPW
SCLK positive or negative pulse width
0.4tCLK
0.6tCLK
ns
tDOHD
(2) (4)
SCLK falling edge to new DOUT invalid (hold time)
10
ns
tDOPD
(2)
SCLK falling edge to new DOUT valid (propagation delay)
31
ns
tDIST
New DIN valid to falling edge of SCLK (setup time)
6
ns
tDIHD
(4)
Old DIN valid to falling edge of SCLK (hold time)
6
ns
(1)
Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK/fDATA).
(2)
Load on DRDY and DOUT = 20pF.
(3)
For best performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8, etc.
(4)
tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4ns.
Copyright © 2007, Texas Instruments Incorporated
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