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ADC10461CIWM Arkusz danych(PDF) 5 Page - National Semiconductor (TI) |
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ADC10461CIWM Arkusz danych(HTML) 5 Page - National Semiconductor (TI) |
5 / 17 page DC Electrical Characteristics The following specifications apply for V + = +5V, V REF(+) =5VVREF(−) = GND, and Speed Adjust pin unconnected unless other- wise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limits) V IN(1) Logical “1” Input Voltage V + = 5.5V 2.0 V (min) V IN(0) Logical “0” Input Voltage V + = 4.5V 0.8 V (max) I IN(1) Logical “1” Input Current V IN(1) = 5V 0.005 3.0 µA (max) I IN(0) Logical “0” Input Current V IN(0) 0V −0.005 −3.0 µA (max) V OUT(1) Logical “1” Output Voltage V + = 4.5V, I OUT = −360 µA 2.4 V (min) V + = 4.5V, I OUT = −10 µA 4.25 V (min) V OUT(0) Logical “0” Output Voltage V + = 4.5V, I OUT = 1.6 mA 0.4 V (max) I OUT TRI-STATE Output Current V OUT =5V V OUT =0V 0.1 −0.1 50 −50 µA (max) µA (max) DI CC DV CC Supply Current CS=S/H=RD=0,R SA = ∞ CS=S/H=RD=0,R SA =18k Ω 1.0 1.0 2 mA (max) mA (max) AI CC AV CC Supply Current CS=S/H=RD=0,R SA = ∞ CS=S/H=RD=0,R SA =18k Ω 30 30 45 mA (max) mA (max) AC Electrical Characteristics The following specifications apply for V + = +5V, t r =tf = 20 ns, VREF(+) = 5V, VREF(−) = GND, and Speed Adjust pin uncon- nected unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C. Symbol Parameter Conditions Typical (Note 7) Limit (Note 8) Units (Limits) t CONV Mode 1 Conversion Time from Rising Edge of S /H to Falling Edge of INT CIN, CIWM Suffixes R SA = 18k 600 375 750/900 ns (max) ns t CRD Mode 2 Conversion Time CIN, CIWM Suffixes Mode 2, R SA = 18k 850 530 1400 ns (max) ns t ACC1 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 1; C L = 100 pF 30 60 ns (max) t ACC2 Access Time (Delay from Falling Edge of RD to Output Valid) Mode 2; C L = 100 pF 900 t CRD +50 ns (max) t SH Minimum Sample Time (Figure 1) ; (Note 9) 250 ns (max) t 1H,t0H TRI-STATE Control (Delay from Rising Edge of RD to High-Z State) R L = 1k, CL =10pF 30 60 ns (max) t INTH Delay from Rising Edge of RD to Rising Edge of INT C L = 100 pF 25 50 ns (max) t P Delay from End of Conversion to Next Conversion 50 ns (max) t MS Multiplexer Control Setup Time 10 75 ns (max) t MH Multiplexer Hold Time 10 40 ns (max) C VIN Analog Input Capacitance 35 pF (max) C OUT Logic Output Capacitance 5 pF (max) C IN Logic Input Capacitance 5 pF (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > V +) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD =(TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. In most cases, the maximum derated power dissipation will be reached only during fault conditions. For these devices, TJMAX for a board-mounted device can be in from the Package Thermal Tables. Note 5: Human body model, 100 pF discharged through a 1.5 k Ω resistor. www.national.com 5 |
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