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74LVC1G386GW Arkusz danych(PDF) 7 Page - NXP Semiconductors

Numer części 74LVC1G386GW
Szczegółowy opis  3-input EXCLUSIVE-OR gate
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Logo NXP - NXP Semiconductors

74LVC1G386GW Arkusz danych(HTML) 7 Page - NXP Semiconductors

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74LVC1G386_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 3 September 2007
7 of 12
NXP Semiconductors
74LVC1G386
3-input EXCLUSIVE-OR gate
Table 9.
Measurement points
VCC
VM
Input
VI
tr = tf
1.65 V to 1.95 V
0.5
× V
CC
VCC
≤ 2.0 ns
2.3 V to 2.7 V
0.5
× VCC
VCC
≤ 2.0 ns
2.7 V
1.5 V
2.7 V
≤ 2.5 ns
3.0 V to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
4.5 V to 5.5 V
0.5
× VCC
VCC
≤ 2.5 ns
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6.
Load circuitry for switching times
VEXT
VCC
VI
VO
mna616
DUT
CL
RT
RL
RL
G
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
30 pF
1 k
open
2.3 V to 2.7 V
VCC
30 pF
500
open
2.7 V
2.7 V
50 pF
500
open
3.0 V to 3.6 V
2.7 V
50 pF
500
open
4.5 V to 5.5 V
VCC
50 pF
500
open


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