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74AUP1G00GW Arkusz danych(PDF) 3 Page - NXP Semiconductors

Numer części 74AUP1G00GW
Szczegółowy opis  Low-power 2-input NAND gate
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Producent  PHILIPS [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AUP1G00GW Arkusz danych(HTML) 3 Page - NXP Semiconductors

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74AUP1G00_2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 29 June 2006
3 of 16
Philips Semiconductors
74AUP1G00
Low-power 2-input NAND gate
6.2 Pin description
7.
Functional description
[1]
H = HIGH voltage level;
L = LOW voltage level.
8.
Limiting values
[1]
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For TSSOP5 packages: above 87.5
°C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
°C the value of Ptot derates linearly with 2.4 mW/K.
Table 3.
Pin description
Symbol
Pin
Description
TSSOP5
XSON6
B
1
1
data input B
A
2
2
data input A
GND
3
3
ground (0 V)
Y
4
4
data output Y
n.c.
-
5
not connected
VCC
5
6
supply voltage
Table 4.
Function table[1]
Input
Output
A
B
Y
LLH
LH
H
HL
H
HHL
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
−0.5
+4.6
V
IIK
input clamping current
VI <0V
-
−50
mA
VI
input voltage
[1]
−0.5
+4.6
V
IOK
output clamping current
VO >VCC or VO <0V
-
±50
mA
VO
output voltage
Active mode
[1]
−0.5
VCC + 0.5
V
Power-down mode
[1]
−0.5
+4.6
V
IO
output current
VO =0 VtoVCC
-
±20
mA
ICC
supply current
-
+50
mA
IGND
ground current
-
−50
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
Tamb = −40 °C to +125 °C
[2] -
250
mW


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