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ADS62P15IRGCT Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS62P15IRGCT Arkusz danych(HTML) 9 Page - Texas Instruments |
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9 / 57 page  www.ti.com TIMING REQUIREMENTS – LVDS AND CMOS MODES (1) ADS62P15 SLAS572 – OCTOBER 2007 Typical values are at 25 °C, min and max values are across the full temperature range T MIN = –40°C to TMAX = 85°C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V, sampling frequency = 125MSPS, sine wave input clock, 3VPP clock amplitude, CLOAD = 5pF (2), Io = 3.5mA, R LOAD = 100Ω (3), no internal termination, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 0.8 1.8 2.8 ns tj Aperture jitter 130 fs rms from global power down 15 50 µs from channel standby 100 200 ns Wake-up time to valid output data from output buffer disable CMOS 100 200 ns LVDS 200 500 ns clock default, after reset 14 cycles clock Latency in low latency mode 10 cycles clock with decimation filter enabled 15 cycles DDR LVDS MODE(4) DRVDD = 3.3V tsu Data setup time(5) Data valid (6) to zero-crossing of CLKOUTP 0.6 1.5 ns th Data hold time(5) Zero-crossing of CLKOUTP to data becoming invalid(6) 1.0 2.3 ns Clock propagation Input clock rising edge cross-over to output clock rising edge cross-over tPDI 3.5 5.5 7.5 ns delay 20 MSPS ≤ Sampling frequency ≤ 125 MSPS LVDS bit clock duty Duty cycle of differential clock, (CLKOUTP-CLKOUTM) 46% 49% 52% cycle 10 MSPS ≤ Sampling frequency ≤ 125 MSPS Rise time measured from –100 mV to +100 mV tRISE Data rise time 70 110 170 ps 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Fall time measured from +100mV to –100 mV tFALL Data fall time 70 110 170 ps 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Rise time measured from –100mV to +100mV tCLKRISE Output clock rise time 70 110 170 ps 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Fall time measured from +100mV to –100mV tCLKFALL Output clock fall time 70 110 170 ps 1 MSPS ≤ Sampling frequency ≤ 125 MSPS PARALLEL CMOS MODE DRVDD = 2.5V to 3.3V tsu Data setup time(5) Data valid(7) to 50% of CLKOUT rising edge 2.0 3.5 ns th Data hold time (5) 50% of CLKOUT rising edge to data becoming invalid(7) 2.0 3.5 ns Clock propagation 50% of input clock rising edge to 50% of CLKOUT rising edge tPDI 5.8 7.3 8.8 ns delay 20 MSPS ≤ Sampling frequency ≤ 125 MSPS Duty cycle of output clock, CLKOUT Output clock duty cycle 45% 53% 60% 10 MSPS ≤ Sampling frequency ≤ 125 MSPS Rise time measured from 20% to 80% of DRVDD tRISE Data rise time 0.7 1.5 2.5 ns 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Fall time measured from 80% to 20% of DRVDD tFALL Data fall time 0.7 1.5 2.5 ns 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE Output clock rise time 0.7 1.5 2.5 ns 1 MSPS ≤ Sampling frequency ≤ 125 MSPS Fall time measured from 80% to 20% of DRVDD tCLKFALL Output clock fall time 0.7 1.5 2.5 ns 1 MSPS ≤ Sampling frequency ≤ 125 MSPS (1) Timing parameters are ensured by design and characterization and not tested in production. (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground (3) IO refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to LOGIC HIGH of +100.0 mV and LOGIC LOW of –100.0mV. (7) Data valid refers to LOGIC HIGH of 2V (1.7V) and LOGIC LOW of 0.8V (0.7V) for DRVDD = 3.3V (2.5V) Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS62P15 |
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