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SM5951AF Arkusz danych(PDF) 11 Page - Nippon Precision Circuits Inc

Numer części SM5951AF
Szczegółowy opis  8-channel DSD Editing System Signal Processor LSI
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Producent  NPC [Nippon Precision Circuits Inc]
Strona internetowa  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

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SM5951A
SEIKO NPC CORPORATION —11
DSD output format
The DSD output format can be set to one of 2 types by the state of SELDSDO.
(1) Normal mode (SELDSDO
= LOW)
DSD output data transitions occur on the falling edge of the bit clock BCKO.
(2) Manchester-type output (SELDSDO
= HIGH)
DSD output data transitions occur on the falling edge of the bit clock BCKO and then inverts on the rising
edge of the bit clock BCKO.
Note. DSDO*: DSDO [8:1] pins, DSD64O*: DSD64O [8:1] pins
MCU Interface
Bus access control
The internal mode and coefficients can be set using either 8/16/32-bit data bus, facilitating easy connection to
various kinds of MCU bus.
The data bus control pins are active LOW. When the chip select (CS_X) is active, read/write control inputs are
valid. When write control (WR_X) is active, data is written in on the rising edge. Data is read out when the read
control (RD_X) is active.
Note. DATA [31:0] pins have an additional bus hold circuit which holds the previous data even when the pin is in a high-impedance ("Hi-Z") state.
DSDO*
D1
D2
BCKO
(1/64fs or 1/128fs)
BCK64O
DSD64O*
DSDO*
D1
D2
BCKO
(1/64fs or 1/128fs)
D1
D2
BCK64O
DSD64O*
ADDR [7:0]
CS_X
RD_X
WR_X
DATA [31:0] (Out)
DATA [31:0] (In)
<Data Read>
<Data Write>
Hi-Z
Hi-Z
Hi-Z
Data (Out)
Data (In)


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