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SM6451A Arkusz danych(PDF) 7 Page - Nippon Precision Circuits Inc |
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SM6451A Arkusz danych(HTML) 7 Page - Nippon Precision Circuits Inc |
7 / 13 page SM6451A SEIKO NPC CORPORATION —7 MICROCONTROLLER INTERFACE The SM6451A uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable) to select channels and attenuation levels for the addressed device. Input Timing The microcontroller data input timing is shown in figure 1. Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK. Note, however, a minimum of 16 MCK input pulses are required. Data Format The format of microcontroller input data is shown in figure 2. D15, D14 Don’t care. D13, D12 Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only when ADRS1:ADRS2 matches D13:D12. Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not addressed since ADRS2 and D12 do not match. Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data is read and the attenuation settings updated. D11, D10 Don’t care. Figure 1. Microcontroller data input timing Figure 2. Microcontroller data format D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MDT MCK MLEN MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 |
Podobny numer części - SM6451A |
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Podobny opis - SM6451A |
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