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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TMP1941AF Arkusz danych(PDF) 6 Page - Toshiba Semiconductor |
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TMP1941AF Arkusz danych(HTML) 6 Page - Toshiba Semiconductor |
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6 / 354 page  TMP1941AF ii 7.7 Port 5 (P50–P57) ............................................................................................................................................. 47 7.8 Port 7 (P70–P77) ............................................................................................................................................. 48 7.9 Port 8 (P80–P87) ............................................................................................................................................. 52 7.10 Port 9 (P90–P97) ............................................................................................................................................. 55 7.11 Port A (PA0–PA7) ........................................................................................................................................... 60 7.12 Open-Drain Output Control ............................................................................................................................. 65 8. External Bus Interface ........................................................................................................................................... 66 8.1 Address and Data Buses .................................................................................................................................. 67 8.1.1 Supported Configurations ....................................................................................................................... 67 8.1.2 States of the Address Bus During On-Chip Address Accesses ............................................................... 67 8.2 External Bus Operation.................................................................................................................................... 68 8.2.1 Basic Bus Operation ............................................................................................................................... 68 8.2.2 Wait Timing ............................................................................................................................................ 69 8.2.3 ALE Pulse Width .................................................................................................................................... 71 8.2.4 Read Recovery Time............................................................................................................................... 72 8.3 Bus Arbitration ................................................................................................................................................ 73 8.3.1 Bus Access Control................................................................................................................................. 73 8.3.2 Bus Arbitration Flow .............................................................................................................................. 73 8.3.3 Relinquishing the bus.............................................................................................................................. 74 9. Chip Select/Wait Controller .................................................................................................................................. 75 9.1 Programming Chip Select Ranges ................................................................................................................... 75 9.1.1 Base/Mask Address Registers (BMA0–BMA3) ..................................................................................... 75 9.1.2 Base Address and Address Mask Value Calculations ............................................................................. 78 9.2 Chip Select/Wait Control Registers ................................................................................................................. 81 9.3 Application Example ....................................................................................................................................... 83 10. DMA Controller (DMAC)..................................................................................................................................... 84 10.1 Features............................................................................................................................................................ 84 10.2 Implementation ................................................................................................................................................ 85 10.2.1 On-Chip DMAC Interface....................................................................................................................... 85 10.2.2 DMAC Block .......................................................................................................................................... 86 10.2.3 Bus Snooping .......................................................................................................................................... 86 10.3 Register Description ........................................................................................................................................ 87 10.3.1 DMA Control Register (DCR) ................................................................................................................ 88 10.3.2 Channel Control Registers (CCRn)......................................................................................................... 89 10.3.3 Channel Status Registers (CSRn)............................................................................................................ 91 10.3.4 Source Address Registers (SARn) .......................................................................................................... 92 10.3.5 Destination Address Registers (DARn) .................................................................................................. 93 10.3.6 Byte Count Registers (BCRn) ................................................................................................................. 94 10.3.7 DMA Transfer Control Registers (DTCRn)............................................................................................ 95 10.3.8 Data Holding Register (DHR)................................................................................................................. 96 10.4 Operation ......................................................................................................................................................... 97 10.4.1 Overview................................................................................................................................................. 97 10.4.2 Transfer Request Generation ................................................................................................................ 100 10.4.3 DMA Address Modes ........................................................................................................................... 101 10.4.4 DMA Channel Operation ...................................................................................................................... 102 10.4.5 DMA Channel Priority.......................................................................................................................... 104 10.4.6 Interrupts............................................................................................................................................... 104 10.4.7 Data Packing and Unpacking ................................................................................................................ 105 10.5 DMA Transfer Timing................................................................................................................................... 106 10.5.1 Dual-Address Mode .............................................................................................................................. 106 10.6 Programming Example .................................................................................................................................. 108 11. 8-Bit Timers (TMRAs)........................................................................................................................................ 109 11.1 Block Diagrams ............................................................................................................................................. 110 11.2 Timer Components ........................................................................................................................................ 112 |
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