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AD5329 Arkusz danych(PDF) 1 Page - Analog Devices |
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AD5329 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 4 page a Two’s Complement Dual, 12-Bit DACs Preliminary Technical Data AD5329 REV PrC, 20 DEC 99 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax:617/326-8703 ©Analog Devices, Inc., 1998 FEATURES • Monotonic DNL < ±1 LSB • Improved Accuracy at Zero Scale • Fast 2 µs Settling Time • Power ON Reset • 3-Wire Serial Data Input • 25MHz Data Load Rate • Internal Reference Voltage • +4.5V to +5.5V Single Supply Operation APPLICATIONS • Digital Control of Gain & Offset GENERAL DESCRIPTION The AD5329 is a serial-input, dual 12-bit digital-to-analog converter that accepts two’s complement digital coding. An internal voltage reference generates a stable 2V DACREF. The buffered DACREF output generates the system bipolar ground reference at pin VBZ. The bipolar DAC output swing programs over a 4VPP range. The device is specified for operation from +5 volts ±10%. Data is loaded MSB first on the positive clock edge (SCLK) when the frame synch (FSYNC) input is active low. The serial clock input word is 16-bits with the MSB position containing an address bit. The last 12 data bits clocked into the register will be transferred to the internal DAC register when the strobe input is returned to logic high. The output transfer equation is: VOUT = [(D-2048) / 4096 * VDACREF] + VBZ Where D is the 12-bit decimal data, and VOUT, VDACREF, VBZ are with respect to ground. The AD5329 is available in the compact 1.1mm thin µSOIC-10 package. All parts are guaranteed to operate over the industrial temperature range of 0°C to +70°C. PIN CONFIGURATION 10 GND 9 SCLK 8 FSYNC 7 NC 6 V BZ V DD 1 SDA 2 NC 3 V OUTB 4 V OUTA 5 ORDERING GUIDE RES Temp Package Package Model (bits) Range Description Option AD5329KRM-REEL7 12 0/+70°C µSOIC-10 RM-10 FUNCTIONAL BLOCK DIAGRAM FSYNC V OUTA DAC A REGISTER 16-Bit SERIAL INPUT REGISTER D11 ...............D0 Power On Reset SCLK SDI GND 12 12 EN V BZ (VREF) V BZ + 2V V BZ - 2V DECODER SW DRIVER A V DD + V DACREF - DAC B REGISTER V OUTB V BZ + 2V V BZ - 2V DECODER SW DRIVER B 12 X2 X2 ADDR DECODE A0 AD5329 +2V |
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