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TMP86FM26UG Arkusz danych(PDF) 6 Page - Toshiba Semiconductor |
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TMP86FM26UG Arkusz danych(HTML) 6 Page - Toshiba Semiconductor |
6 / 242 page ii 3.3.1 Interrupt acceptance processing is packaged as follows........................................................................ 45 3.3.2 Saving/restoring general-purpose registers............................................................................................ 46 3.3.2.1 Using PUSH and POP instructions 3.3.2.2 Using data transfer instructions 3.3.3 Interrupt return ........................................................................................................................................ 47 3.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.4.1 Address error detection .......................................................................................................................... 48 3.4.2 Debugging .............................................................................................................................................. 48 3.5 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4. Special Function Register (SFR) 4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5. I/O Ports 5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.2 Port P2 (P24 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3 Port P3 (P33 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.4 Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.5 Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.6 Port P7(P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6. Watchdog Timer (WDT) 6.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.2.1 Malfunction Detection Methods Using the Watchdog Timer................................................................... 72 6.2.2 Watchdog Timer Enable ......................................................................................................................... 73 6.2.3 Watchdog Timer Disable ........................................................................................................................ 74 6.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 74 6.2.5 Watchdog Timer Reset ........................................................................................................................... 75 6.3 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.1 Selection of Address Trap in Internal RAM (ATAS)................................................................................ 76 6.3.2 Selection of Operation at Address Trap (ATOUT) .................................................................................. 76 6.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 76 6.3.4 Address Trap Reset................................................................................................................................ 77 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1.1 Configuration .......................................................................................................................................... 79 7.1.2 Control .................................................................................................................................................... 79 7.1.3 Function .................................................................................................................................................. 80 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.2.1 Configuration .......................................................................................................................................... 81 7.2.2 Control .................................................................................................................................................... 81 |
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