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TA1275BFNG Arkusz danych(PDF) 5 Page - Toshiba Semiconductor |
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TA1275BFNG Arkusz danych(HTML) 5 Page - Toshiba Semiconductor |
5 / 21 page TA1275BFNG 2005-03-14 5 Terminal Interface The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Pin No. Pin Name Function Interface Circuit Input/Output Signal 1 SCP IN The pin for inputting the sand castle pulse (SCP) 1 18 2 ― 2 Vcc 5 V (Pulse) VCC pin for logic block ― ― 3 N.C. (No Connection) Connect to GND. ― ― 4 4.43CW-IN GATE WIDTH The pin for inputting 4.43 MHz of carrier wave for the selfadjustment circuit. Input a 500 mVp-p sine wave through a coupling capacitor. The switch for changing the gate pulse width is overlaid on this pin. +200 nS : to VCC thru 33 kΩ 0ns : open −200 nS : to GND thru 33 kΩ 4 18 15 ― |
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